a99f02d0ee
The driver backend is capable of supporting also ISA cards (no DMA) and primary rate (PRI) cards in addition to the basic rate ones, but I don't any to test on right now, so we don't support those currently. This code was originally written by Juha-Matti Liukkonen <jml@cubical.fi> of Cubical Solutions Ltd. for FreeBSD, and was ported to NetBSD by myself for the same company.
484 lines
13 KiB
C
484 lines
13 KiB
C
/* $NetBSD: iavcreg.h,v 1.1 2003/09/25 15:53:26 pooka Exp $ */
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/*
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* Copyright (c) 2001-2003 Cubical Solutions Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* capi/iavc/iavc.h The AVM ISDN controllers' common declarations.
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*
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* $FreeBSD: src/sys/i4b/capi/iavc/iavc.h,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
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*/
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/*
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// AMCC_{READ,WRITE}
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// Routines to access the memory mapped registers of the
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// S5933 DMA controller.
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*/
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static __inline u_int32_t AMCC_READ(iavc_softc_t *sc, int off)
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{
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return bus_space_read_4(sc->sc_mem_bt, sc->sc_mem_bh, off);
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}
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static __inline void AMCC_WRITE(iavc_softc_t *sc, int off, u_int32_t value)
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{
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bus_space_write_4(sc->sc_mem_bt, sc->sc_mem_bh, off, value);
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}
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/*
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// amcc_{put,get}_{byte,word}
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// Routines to access the DMA buffers byte- or wordwise.
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*/
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static __inline u_int8_t* amcc_put_byte(u_int8_t *buf, u_int8_t value)
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{
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*buf++ = value;
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return buf;
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}
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static __inline u_int8_t* amcc_get_byte(u_int8_t *buf, u_int8_t *value)
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{
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*value = *buf++;
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return buf;
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}
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static __inline u_int8_t* amcc_put_word(u_int8_t *buf, u_int32_t value)
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{
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*buf++ = (value & 0xff);
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*buf++ = (value >> 8) & 0xff;
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*buf++ = (value >> 16) & 0xff;
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*buf++ = (value >> 24) & 0xff;
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return buf;
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}
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static __inline u_int8_t* amcc_get_word(u_int8_t *buf, u_int32_t *value)
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{
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*value = *buf++;
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*value |= (*buf++ << 8);
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*value |= (*buf++ << 16);
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*value |= (*buf++ << 24);
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return buf;
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}
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/*
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// Controller LLI message numbers.
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*/
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#define SEND_POLL 0x72
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#define SEND_INIT 0x11
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#define SEND_REGISTER 0x12
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#define SEND_DATA_B3_REQ 0x13
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#define SEND_RELEASE 0x14
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#define SEND_MESSAGE 0x15
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#define SEND_CONFIG 0x71
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#define SEND_POLLACK 0x73
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#define RECEIVE_POLL 0x32
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#define RECEIVE_INIT 0x27
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#define RECEIVE_MESSAGE 0x21
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#define RECEIVE_DATA_B3_IND 0x22
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#define RECEIVE_START 0x23
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#define RECEIVE_STOP 0x24
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#define RECEIVE_NEW_NCCI 0x25
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#define RECEIVE_FREE_NCCI 0x26
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#define RECEIVE_RELEASE 0x26
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#define RECEIVE_TASK_READY 0x31
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#define RECEIVE_DEBUGMSG 0x71
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#define RECEIVE_POLLDWORD 0x75
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/* Operation constants */
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#define WRITE_REGISTER 0x00
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#define READ_REGISTER 0x01
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/* Port offsets in I/O space */
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#define B1_READ 0x00
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#define B1_WRITE 0x01
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#define B1_INSTAT 0x02
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#define B1_OUTSTAT 0x03
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#define B1_ANALYSE 0x04
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#define B1_REVISION 0x05
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#define B1_RESET 0x10
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#define T1_FASTLINK 0x00
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#define T1_SLOWLINK 0x08
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#define T1_READ B1_READ
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#define T1_WRITE B1_WRITE
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#define T1_INSTAT B1_INSTAT
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#define T1_OUTSTAT B1_OUTSTAT
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#define T1_IRQENABLE 0x05
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#define T1_FIFOSTAT 0x06
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#define T1_RESETLINK 0x10
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#define T1_ANALYSE 0x11
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#define T1_IRQMASTER 0x12
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#define T1_IDENT 0x17
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#define T1_RESETBOARD 0x1f
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#define T1F_IREADY 0x01
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#define T1F_IHALF 0x02
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#define T1F_IFULL 0x04
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#define T1F_IEMPTY 0x08
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#define T1F_IFLAGS 0xf0
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#define T1F_OREADY 0x10
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#define T1F_OHALF 0x20
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#define T1F_OEMPTY 0x40
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#define T1F_OFULL 0x80
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#define T1F_OFLAGS 0xf0
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#define FIFO_OUTBSIZE 256
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#define FIFO_INPBSIZE 512
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#define HEMA_VERSION_ID 0
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#define HEMA_PAL_ID 0
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/*
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// S5933 DMA controller register offsets in memory, and bitmasks.
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*/
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#define AMCC_RXPTR 0x24
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#define AMCC_RXLEN 0x28
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#define AMCC_TXPTR 0x2c
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#define AMCC_TXLEN 0x30
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#define AMCC_INTCSR 0x38
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#define EN_READ_TC_INT 0x00008000
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#define EN_WRITE_TC_INT 0x00004000
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#define EN_TX_TC_INT EN_READ_TC_INT
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#define EN_RX_TC_INT EN_WRITE_TC_INT
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#define AVM_FLAG 0x30000000
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#define ANY_S5933_INT 0x00800000
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#define READ_TC_INT 0x00080000
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#define WRITE_TC_INT 0x00040000
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#define TX_TC_INT READ_TC_INT
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#define RX_TC_INT WRITE_TC_INT
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#define MASTER_ABORT_INT 0x00100000
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#define TARGET_ABORT_INT 0x00200000
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#define BUS_MASTER_INT 0x00200000
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#define ALL_INT 0x000c0000
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#define AMCC_MCSR 0x3c
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#define A2P_HI_PRIORITY 0x00000100
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#define EN_A2P_TRANSFERS 0x00000400
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#define P2A_HI_PRIORITY 0x00001000
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#define EN_P2A_TRANSFERS 0x00004000
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#define RESET_A2P_FLAGS 0x04000000
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#define RESET_P2A_FLAGS 0x02000000
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/*
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// (B1IO_WAIT_MAX * B1IO_WAIT_DLY) is the max wait in us for the card
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// to become ready after an I/O operation. The default is 1 ms.
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*/
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#define B1IO_WAIT_MAX 1000
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#define B1IO_WAIT_DLY 1
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/*
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// b1io_outp
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// Diagnostic output routine, returns the written value via
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// the device's analysis register.
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//
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// b1io_rx_full
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// Returns nonzero if data is readable from the card via the
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// I/O ports.
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//
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// b1io_tx_empty
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// Returns nonzero if data can be written to the card via the
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// I/O ports.
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*/
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static __inline u_int8_t b1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
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{
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bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
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DELAY(1);
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return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_ANALYSE);
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}
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static __inline int b1io_rx_full(iavc_softc_t *sc)
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{
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u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_INSTAT);
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return (val & 0x01);
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}
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static __inline int b1io_tx_empty(iavc_softc_t *sc)
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{
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u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_OUTSTAT);
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return (val & 0x01);
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}
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/*
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// b1io_{get,put}_{byte,word}
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// Routines to read and write the device I/O registers byte- or
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// wordwise.
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//
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// b1io_{get,put}_slice
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// Routines to read and write sequential bytes to the device
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// I/O registers.
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*/
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static __inline u_int8_t b1io_get_byte(iavc_softc_t *sc)
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{
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int spin = 0;
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while (!b1io_rx_full(sc) && spin < B1IO_WAIT_MAX) {
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spin++; DELAY(B1IO_WAIT_DLY);
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}
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if (b1io_rx_full(sc))
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return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_READ);
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printf("iavc%d: rx not completed\n", sc->sc_unit);
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return 0xff;
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}
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static __inline int b1io_put_byte(iavc_softc_t *sc, u_int8_t val)
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{
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int spin = 0;
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while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
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spin++; DELAY(B1IO_WAIT_DLY);
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}
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if (b1io_tx_empty(sc)) {
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bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, B1_WRITE, val);
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return 0;
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}
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printf("iavc%d: tx not emptied\n", sc->sc_unit);
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return -1;
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}
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static __inline int b1io_save_put_byte(iavc_softc_t *sc, u_int8_t val)
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{
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int spin = 0;
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while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
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spin++; DELAY(B1IO_WAIT_DLY);
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}
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if (b1io_tx_empty(sc)) {
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b1io_outp(sc, B1_WRITE, val);
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return 0;
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}
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printf("iavc%d: tx not emptied\n", sc->sc_unit);
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return -1;
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}
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static __inline u_int32_t b1io_get_word(iavc_softc_t *sc)
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{
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u_int32_t val = 0;
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val |= b1io_get_byte(sc);
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val |= (b1io_get_byte(sc) << 8);
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val |= (b1io_get_byte(sc) << 16);
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val |= (b1io_get_byte(sc) << 24);
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return val;
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}
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static __inline void b1io_put_word(iavc_softc_t *sc, u_int32_t val)
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{
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b1io_put_byte(sc, (val & 0xff));
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b1io_put_byte(sc, (val >> 8) & 0xff);
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b1io_put_byte(sc, (val >> 16) & 0xff);
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b1io_put_byte(sc, (val >> 24) & 0xff);
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}
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static __inline int b1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
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{
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int len, i;
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len = i = b1io_get_word(sc);
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while (i--) *dp++ = b1io_get_byte(sc);
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return len;
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}
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static __inline void b1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
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{
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b1io_put_word(sc, len);
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while (len--) b1io_put_byte(sc, *dp++);
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}
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/*
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// b1io_{read,write}_reg
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// Routines to read and write the device registers via the I/O
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// ports.
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*/
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static __inline u_int32_t b1io_read_reg(iavc_softc_t *sc, int reg)
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{
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b1io_put_byte(sc, READ_REGISTER);
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b1io_put_word(sc, reg);
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return b1io_get_word(sc);
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}
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static __inline u_int32_t b1io_write_reg(iavc_softc_t *sc, int reg, u_int32_t val)
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{
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b1io_put_byte(sc, WRITE_REGISTER);
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b1io_put_word(sc, reg);
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b1io_put_word(sc, val);
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return b1io_get_word(sc);
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}
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/*
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// t1io_outp
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// I/O port write operation for the T1, which does not seem
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// to have the analysis port.
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*/
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static __inline void t1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
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{
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bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
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}
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static __inline u_int8_t t1io_inp(iavc_softc_t *sc, int off)
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{
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return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, off);
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}
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static __inline int t1io_isfastlink(iavc_softc_t *sc)
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{
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return ((bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_IDENT) & ~0x82) == 1);
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}
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static __inline u_int8_t t1io_fifostatus(iavc_softc_t *sc)
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{
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return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_FIFOSTAT);
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}
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static __inline int t1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
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{
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int len, i;
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len = i = b1io_get_word(sc);
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if (t1io_isfastlink(sc)) {
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int status;
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while (i) {
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status = t1io_fifostatus(sc) & (T1F_IREADY|T1F_IHALF);
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if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
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switch (status) {
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case T1F_IREADY|T1F_IHALF|T1F_IFULL:
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bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
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T1_READ, dp, FIFO_INPBSIZE);
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dp += FIFO_INPBSIZE;
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i -= FIFO_INPBSIZE;
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break;
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case T1F_IREADY|T1F_IHALF:
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bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
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T1_READ, dp, i);
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dp += i;
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i = 0;
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break;
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default:
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*dp++ = b1io_get_byte(sc);
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i--;
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}
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}
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} else { /* not fastlink */
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if (i--) *dp++ = b1io_get_byte(sc);
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}
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return len;
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}
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static __inline void t1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
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{
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int i = len;
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b1io_put_word(sc, i);
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if (t1io_isfastlink(sc)) {
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int status;
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while (i) {
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status = t1io_fifostatus(sc) & (T1F_OREADY|T1F_OHALF);
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if (i >= FIFO_OUTBSIZE) status |= T1F_OFULL;
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switch (status) {
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case T1F_OREADY|T1F_OHALF|T1F_OFULL:
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bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
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T1_WRITE, dp, FIFO_OUTBSIZE);
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dp += FIFO_OUTBSIZE;
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i -= FIFO_OUTBSIZE;
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break;
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case T1F_OREADY|T1F_OHALF:
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bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
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T1_WRITE, dp, i);
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dp += i;
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i = 0;
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break;
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default:
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b1io_put_byte(sc, *dp++);
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i--;
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}
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}
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} else {
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while (i--) b1io_put_byte(sc, *dp++);
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}
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}
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/*
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// An attempt to bring it all together:
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// ------------------------------------
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//
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// iavc_{read,write}_reg
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// Routines to access the device registers via the I/O port.
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//
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// iavc_{read,write}_port
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// Routines to access the device I/O ports.
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//
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// iavc_tx_empty, iavc_rx_full
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// Routines to check when the device has drained the last written
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// byte, or produced a full byte to read.
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//
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// iavc_{get,put}_byte
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// Routines to read/write byte values to the device via the I/O port.
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//
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// iavc_{get,put}_word
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// Routines to read/write 32-bit words to the device via the I/O port.
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//
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// iavc_{get,put}_slice
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// Routines to read/write {length, data} pairs to the device via the
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// ubiquituous I/O port. Uses the HEMA FIFO on a T1.
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*/
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#define iavc_read_reg(sc, reg) b1io_read_reg(sc, reg)
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#define iavc_write_reg(sc, reg, val) b1io_write_reg(sc, reg, val)
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#define iavc_read_port(sc, port) \
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bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, (port))
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#define iavc_write_port(sc, port, val) \
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bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, (port), (val))
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#define iavc_tx_empty(sc) b1io_tx_empty(sc)
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#define iavc_rx_full(sc) b1io_rx_full(sc)
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#define iavc_get_byte(sc) b1io_get_byte(sc)
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#define iavc_put_byte(sc, val) b1io_put_byte(sc, val)
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#define iavc_get_word(sc) b1io_get_word(sc)
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#define iavc_put_word(sc, val) b1io_put_word(sc, val)
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static __inline u_int32_t iavc_get_slice(iavc_softc_t *sc, u_int8_t *dp)
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{
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if (sc->sc_t1) return t1io_get_slice(sc, dp);
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else return b1io_get_slice(sc, dp);
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}
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static __inline void iavc_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
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{
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if (sc->sc_t1) t1io_put_slice(sc, dp, len);
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else b1io_put_slice(sc, dp, len);
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}
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