163 lines
6.0 KiB
C
163 lines
6.0 KiB
C
/* $NetBSD: if_gfevar.h,v 1.6 2005/02/27 00:27:21 perry Exp $ */
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/*
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* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Allegro Networks, Inc., and Wasabi Systems, Inc.
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* 4. The name of Allegro Networks, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* 5. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
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* WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define GE_RXDESC_MEMSIZE (1 * PAGE_SIZE)
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#define GE_RXDESC_MAX 64
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#define GE_RXBUF_SIZE 2048
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#define GE_RXBUF_MEMSIZE (GE_RXDESC_MAX*GE_RXBUF_SIZE)
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#define GE_RXBUF_NSEGS ((GE_RXBUF_MEMSIZE/PAGE_SIZE)+1)
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#define GE_DMSEG_MAX (GE_RXBUF_NSEGS)
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struct gfe_dmamem {
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bus_dmamap_t gdm_map; /* dmamem'ed memory */
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caddr_t gdm_kva; /* kva of tx memory */
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int gdm_nsegs; /* # of segment in gdm_segs */
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int gdm_maxsegs; /* maximum # of segments allowed */
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size_t gdm_size; /* size of memory region */
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bus_dma_segment_t gdm_segs[GE_DMSEG_MAX]; /* dma segment of tx memory */
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};
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/* With a 4096 page size, we get 256 descriptors per page.
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*/
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#define GE_TXDESC_MEMSIZE (1 * PAGE_SIZE)
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#define GE_TXDESC_MAX (GE_TXDESC_MEMSIZE / 16)
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#define GE_TXBUF_SIZE (4 * PAGE_SIZE)
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struct gfe_txqueue {
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struct ifqueue txq_pendq; /* these are ready to go to the GT */
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struct gfe_dmamem txq_desc_mem; /* transmit descriptor memory */
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struct gfe_dmamem txq_buf_mem; /* transmit buffer memory */
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unsigned int txq_lo; /* next to be given to GT */
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unsigned int txq_fi; /* next to be returned to CPU */
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unsigned int txq_ei_gapcount; /* counter until next EI */
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unsigned int txq_nactive; /* number of active descriptors */
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unsigned int txq_outptr; /* where to put next transmit packet */
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unsigned int txq_inptr; /* start of 1st queued tx packet */
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uint32_t txq_intrbits; /* bits to write to EIMR */
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uint32_t txq_esdcmrbits; /* bits to write to ESDCMR */
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uint32_t txq_epsrbits; /* bits to test with EPSR */
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volatile struct gt_eth_desc *txq_descs; /* ptr to tx descriptors */
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bus_addr_t txq_ectdp; /* offset to cur. tx desc ptr reg */
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bus_addr_t txq_desc_busaddr; /* bus addr of tx descriptors */
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bus_addr_t txq_buf_busaddr; /* bus addr of tx buffers */
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};
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/* With a 4096 page size, we get 256 descriptors per page. We want 1024
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* which will give us about 8ms of 64 byte packets (2ms for each priority
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* queue).
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*/
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struct gfe_rxbuf {
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uint8_t rb_data[GE_RXBUF_SIZE];
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};
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struct gfe_rxqueue {
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struct gfe_dmamem rxq_desc_mem; /* receive descriptor memory */
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struct gfe_dmamem rxq_buf_mem; /* receive buffer memory */
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struct mbuf *rxq_curpkt; /* mbuf for current packet */
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volatile struct gt_eth_desc *rxq_descs;
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struct gfe_rxbuf *rxq_bufs;
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unsigned int rxq_fi; /* next to be returned to CPU */
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unsigned int rxq_active; /* # of descriptors given to GT */
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uint32_t rxq_intrbits; /* bits to write to EIMR */
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bus_addr_t rxq_desc_busaddr; /* bus addr of rx descriptors */
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uint32_t rxq_cmdsts; /* save cmdsts from first descriptor */
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bus_size_t rxq_efrdp;
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bus_size_t rxq_ecrdp;
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};
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enum gfe_txprio {
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GE_TXPRIO_HI=1,
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GE_TXPRIO_LO=0,
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GE_TXPRIO_NONE=2
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};
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enum gfe_rxprio {
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GE_RXPRIO_HI=3,
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GE_RXPRIO_MEDHI=2,
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GE_RXPRIO_MEDLO=1,
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GE_RXPRIO_LO=0
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};
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struct gfe_softc {
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struct device sc_dev; /* must be first */
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struct ethercom sc_ec; /* common ethernet glue */
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struct callout sc_co; /* resource recovery */
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mii_data_t sc_mii; /* mii interface */
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/*
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*
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*/
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bus_space_tag_t sc_gt_memt;
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bus_space_handle_t sc_gt_memh;
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bus_space_handle_t sc_memh; /* subregion for ethernet */
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bus_dma_tag_t sc_dmat;
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int sc_macno; /* which mac? 0, 1, or 2 */
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unsigned int sc_tickflags;
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#define GE_TICK_TX_IFSTART 0x0001
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#define GE_TICK_RX_RESTART 0x0002
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unsigned int sc_flags;
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#define GE_ALLMULTI 0x0001
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#define GE_PHYSTSCHG 0x0002
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#define GE_RXACTIVE 0x0004
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#define GE_NOFREE 0x0008 /* Don't free on disable */
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uint32_t sc_pcr; /* current EPCR value */
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uint32_t sc_pcxr; /* current EPCXR value */
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uint32_t sc_intrmask; /* current EIMR value */
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uint32_t sc_idlemask; /* suspended EIMR bits */
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size_t sc_max_frame_length; /* maximum frame length */
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/*
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* Hash table related members
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*/
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struct gfe_dmamem sc_hash_mem; /* dma'ble hash table */
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uint64_t *sc_hashtable;
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unsigned int sc_hashmask; /* 0x1ff or 0x1fff */
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/*
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* Transmit related members
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*/
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struct gfe_txqueue sc_txq[2]; /* High & Low transmit queues */
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/*
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* Receive related members
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*/
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struct gfe_rxqueue sc_rxq[4]; /* Hi/MedHi/MedLo/Lo receive queues */
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};
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