07b064e02e
Some of the stuff (e.g., rarpd, bootpd, dhcpd etc., libsa) still will only support Ethernet. Tcpdump itself should be ok, but libpcap needs lot of work. For the detailed change history, look at the commit log entries for the is-newarp branch.
381 lines
7.0 KiB
ArmAsm
381 lines
7.0 KiB
ArmAsm
/* $NetBSD: icside_io_asm.S,v 1.2 1997/03/15 18:09:35 is Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* bus_space I/O functions for ICS IDE podule
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*/
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sp .req r13
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lr .req r14
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pc .req r15
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.text
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/*
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* read single
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*/
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.global _icside_r_1
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_icside_r_1:
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ldrb r0, [r1, r2, lsl #6]
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mov pc, lr
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.global _icside_r_2
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_icside_r_2:
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ldr r0, [r1, r2, lsl #6]
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bic r0, r0, #0xff000000
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bic r0, r0, #0x00ff0000
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mov pc, lr
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.global _icside_r_4
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_icside_r_4:
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ldr r0, [r1, r2, lsl #6]
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mov pc, lr
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.global _icside_r_8
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_icside_r_8:
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adr r0, icside_r_8_text
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b _panic
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icside_r_8_text:
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.asciz "icside_r_8(%x,%x): Not implemented\n"
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.align 0
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/*
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* write single
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*/
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.global _icside_w_1
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_icside_w_1:
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strb r3, [r1, r2, lsl #6]
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mov pc, lr
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.global _icside_w_2
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_icside_w_2:
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mov r3, r3, lsl #16
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orr r3, r3, r3, lsr #16
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str r3, [r1, r2, lsl #6]
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mov pc, lr
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.global _icside_w_4
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_icside_w_4:
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str r3, [r1, r2, lsl #6]
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mov pc, lr
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.global _icside_w_8
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_icside_w_8:
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adr r0, icside_w_8_text
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b _panic
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icside_w_8_text:
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.asciz "icside_w_8(%x,%x,%x): Not implemented\n"
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.align 0
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/*
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* read multiple
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*/
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.global _icside_rm_1
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_icside_rm_1:
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adr r0, icside_rm_1_text
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b _panic
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icside_rm_1_text:
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.asciz "icside_rm_1(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_rm_2
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_icside_rm_2:
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add r0, r1, r2, lsl #6
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mov r1, r3
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ldr r2, [sp, #0]
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b _inswm8
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.global _icside_rm_4
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_icside_rm_4:
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adr r0, icside_rm_4_text
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b _panic
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icside_rm_4_text:
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.asciz "icside_rm_4(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_rm_8
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_icside_rm_8:
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adr r0, icside_rm_8_text
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b _panic
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icside_rm_8_text:
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.asciz "icside_rm_8(%x,%x,%x,%x): Not implemented\n"
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.align 0
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/*
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* write multiple
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*/
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.global _icside_wm_1
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_icside_wm_1:
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adr r0, icside_wm_1_text
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b _panic
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icside_wm_1_text:
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.asciz "icside_wm_1(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_wm_2
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_icside_wm_2:
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add r0, r1, r2, lsl #6
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mov r1, r3
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ldr r2, [sp, #0]
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b _outswm8
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.global _icside_wm_4
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_icside_wm_4:
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adr r0, icside_wm_4_text
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b _panic
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icside_wm_4_text:
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.asciz "icside_wm_4(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_wm_8
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_icside_wm_8:
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adr r0, icside_wm_8_text
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b _panic
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icside_wm_8_text:
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.asciz "icside_wm_8(%x,%x,%x,%x): Not implemented\n"
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.align 0
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/*
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* read region
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*/
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.global _icside_rr_1
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_icside_rr_1:
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adr r0, icside_rr_1_text
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b _panic
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icside_rr_1_text:
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.asciz "icside_rr_1(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_rr_2
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_icside_rr_2:
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adr r0, icside_rr_2_text
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b _panic
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icside_rr_2_text:
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.asciz "icside_rr_2(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_rr_4
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_icside_rr_4:
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adr r0, icside_rr_4_text
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b _panic
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icside_rr_4_text:
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.asciz "icside_rr_4(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_rr_8
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_icside_rr_8:
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adr r0, icside_rr_8_text
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b _panic
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icside_rr_8_text:
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.asciz "icside_rr_8(%x,%x,%x,%x): Not implemented\n"
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.align 0
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/*
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* write region
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*/
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.global _icside_wr_1
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_icside_wr_1:
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adr r0, icside_wr_1_text
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b _panic
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icside_wr_1_text:
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.asciz "icside_wr_1(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_wr_2
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_icside_wr_2:
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adr r0, icside_wr_2_text
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b _panic
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icside_wr_2_text:
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.asciz "icside_wr_2(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_wr_4
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_icside_wr_4:
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adr r0, icside_wr_4_text
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b _panic
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icside_wr_4_text:
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.asciz "icside_wr_4(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_wr_8
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_icside_wr_8:
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adr r0, icside_wr_8_text
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b _panic
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icside_wr_8_text:
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.asciz "icside_wr_8(%x,%x,%x,%x): Not implemented\n"
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.align 0
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/*
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* set multiple
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*/
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.global _icside_sm_1
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_icside_sm_1:
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adr r0, icside_sm_1_text
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b _panic
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icside_sm_1_text:
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.asciz "icside_sm_1(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_sm_2
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_icside_sm_2:
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adr r0, icside_sm_2_text
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b _panic
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icside_sm_2_text:
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.asciz "icside_sm_2(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_sm_4
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_icside_sm_4:
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adr r0, icside_sm_4_text
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b _panic
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icside_sm_4_text:
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.asciz "icside_sm_4(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_sm_8
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_icside_sm_8:
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adr r0, icside_sm_8_text
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b _panic
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icside_sm_8_text:
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.asciz "icside_sm_8(%x,%x,%x,%x): Not implemented\n"
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.align 0
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/*
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* set region
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*/
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.global _icside_sr_1
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_icside_sr_1:
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adr r0, icside_sr_1_text
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b _panic
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icside_sr_1_text:
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.asciz "icside_sr_1(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_sr_2
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_icside_sr_2:
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adr r0, icside_sr_2_text
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b _panic
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icside_sr_2_text:
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.asciz "icside_sr_2(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_sr_4
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_icside_sr_4:
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adr r0, icside_sr_4_text
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b _panic
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icside_sr_4_text:
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.asciz "icside_sr_4(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_sr_8
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_icside_sr_8:
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adr r0, icside_sr_8_text
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b _panic
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icside_sr_8_text:
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.asciz "icside_sr_8(%x,%x,%x,%x): Not implemented\n"
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.align 0
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/*
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* copy
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*/
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.global _icside_c_1
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_icside_c_1:
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adr r0, icside_c_1_text
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b _panic
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icside_c_1_text:
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.asciz "icside_c_1(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_c_2
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_icside_c_2:
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adr r0, icside_c_2_text
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b _panic
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icside_c_2_text:
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.asciz "icside_c_2(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_c_4
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_icside_c_4:
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adr r0, icside_c_4_text
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b _panic
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icside_c_4_text:
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.asciz "icside_c_4(%x,%x,%x,%x): Not implemented\n"
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.align 0
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.global _icside_c_8
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_icside_c_8:
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adr r0, icside_c_8_text
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b _panic
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icside_c_8_text:
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.asciz "icside_c_8(%x,%x,%x,%x): Not implemented\n"
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.align 0
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