265 lines
8.1 KiB
C
265 lines
8.1 KiB
C
/* $NetBSD: logout.h,v 1.3 2001/03/25 05:52:38 nathanw Exp $ */
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/*
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* Copyright (c) 1998 by Matthew Jacob
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* NASA AMES Research Center.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Various Alpha OSF/1 PAL Logout error defintions.
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*/
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/*
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* Information gathered from: DEC documentation
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*/
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/*
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* Avanti (AlphaStation 200 and 400) Specific PALcode Exception Logout
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* Area Definitions
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*/
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/*
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* Avanti Specific common logout frame header.
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* *Almost* identical to the generic logout header listed in alpha_cpu.h.
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*/
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typedef struct {
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unsigned int la_frame_size; /* frame size */
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unsigned int la_flags; /* flags; see alpha_cpu.h */
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unsigned int la_cpu_offset; /* offset to cpu area */
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unsigned int la_system_offset; /* offset to system area */
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unsigned long mcheck_code; /* machine check code */
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} mc_hdr_avanti;
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/* Machine Check Codes */
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/* SCB 660 Fatal Machine Checks */
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#define AVANTI_RETRY_TIMEOUT 0x201L
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#define AVANTI_DMA_DATA_PARITY 0x202L
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#define AVANTI_IO_PARITY 0x203L
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#define AVANTI_TARGET_ABORT 0x204L
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#define AVANTI_NO_DEVICE 0x205L
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#define AVANTI_CORRRECTABLE_MEMORY 0x206L /* Should never occur */
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#define AVANTI_UNCORRECTABLE_PCI_MEMORY 0x207L
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#define AVANTI_INVALID_PT_LOOKUP 0x208L
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#define AVANTI_MEMORY 0x209L
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#define AVANTI_BCACHE_TAG_ADDR_PARITY 0x20AL
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#define AVANTI_BCACHE_TAG_CTRL_PARITY 0x20BL
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#define AVANTI_NONEXISTENT_MEMORY 0x20CL
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#define AVANTI_IO_BUS 0x20DL
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#define AVANTI_BCACHE_TAG_PARITY 0x80L
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#define AVANTI_BCACHE_TAG_CTRL_PARITY2 0x82L
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/* SCB 670 Processor Fatal Machine Checks */
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#define AVANTI_HARD_ERROR 0x84L
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#define AVANTI_CORRECTABLE_ECC 0x86L
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#define AVANTI_NONCORRECTABLE_ECC 0x88L
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#define AVANTI_UNKNOWN_ERROR 0x8AL
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#define AVANTI_SOFT_ERROR 0x8CL
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#define AVANTI_BUGCHECK 0x8EL
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#define AVANTI_OS_BUGCHECK 0x90L
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#define AVANTI_DCACHE_FILL_PARITY 0x92L
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#define AVANTI_ICACHE_FILL_PARITY 0x94L
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typedef struct {
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/* Registers from the CPU */
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u_int64_t paltemp[32]; /* PAL TEMP REGS. */
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u_int64_t exc_addr; /* Address of excepting ins. */
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u_int64_t exc_sum; /* Summary of arithmetic traps. */
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u_int64_t exc_mask; /* Exception mask. */
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u_int64_t iccsr;
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u_int64_t pal_base; /* Base address for PALcode. */
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u_int64_t hier;
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u_int64_t hirr;
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u_int64_t mm_csr;
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u_int64_t dc_stat;
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u_int64_t dc_addr;
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u_int64_t abox_ctl;
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u_int64_t biu_stat; /* Bus Interface Unit Status. */
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u_int64_t biu_addr;
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u_int64_t biu_ctl;
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u_int64_t fill_syndrome;
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u_int64_t fill_addr;
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u_int64_t va;
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u_int64_t bc_tag;
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/* Registers from the cache and memory controller (21071-CA) */
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u_int64_t coma_gcr; /* Error and Diag. Status. */
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u_int64_t coma_edsr;
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u_int64_t coma_ter;
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u_int64_t coma_elar;
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u_int64_t coma_ehar;
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u_int64_t coma_ldlr;
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u_int64_t coma_ldhr;
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u_int64_t coma_base0;
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u_int64_t coma_base1;
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u_int64_t coma_base2;
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u_int64_t coma_cnfg0;
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u_int64_t coma_cnfg1;
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u_int64_t coma_cnfg2;
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/* Registers from the PCI bridge (21071-DA) */
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u_int64_t epic_dcsr; /* Diag. Control and Status. */
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u_int64_t epic_pear;
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u_int64_t epic_sear;
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u_int64_t epic_tbr1;
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u_int64_t epic_tbr2;
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u_int64_t epic_pbr1;
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u_int64_t epic_pbr2;
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u_int64_t epic_pmr1;
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u_int64_t epic_pmr2;
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u_int64_t epic_harx1;
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u_int64_t epic_harx2;
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u_int64_t epic_pmlt;
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u_int64_t epic_tag0;
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u_int64_t epic_tag1;
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u_int64_t epic_tag2;
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u_int64_t epic_tag3;
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u_int64_t epic_tag4;
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u_int64_t epic_tag5;
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u_int64_t epic_tag6;
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u_int64_t epic_tag7;
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u_int64_t epic_data0;
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u_int64_t epic_data1;
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u_int64_t epic_data2;
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u_int64_t epic_data3;
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u_int64_t epic_data4;
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u_int64_t epic_data5;
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u_int64_t epic_data6;
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u_int64_t epic_data7;
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} mc_uc_avanti;
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/*
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* Information gathered from: OSF/1 header files.
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*/
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/*
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* EV5 Specific OSF/1 Pal Code Exception Logout Area Definitions
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* (inspired from OSF/1 Header files).
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*/
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/*
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* EV5 Specific common logout frame header.
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* *Almost* identical to the generic logout header listed in alpha_cpu.h.
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*/
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typedef struct {
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unsigned int la_frame_size; /* frame size */
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unsigned int la_flags; /* flags; see alpha_cpu.h */
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unsigned int la_cpu_offset; /* offset to cpu area */
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unsigned int la_system_offset; /* offset to system area */
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unsigned long mcheck_code; /* machine check code */
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} mc_hdr_ev5;
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/* Machine Check Codes */
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#define EV5_CORRECTED 0x86L
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#define SYSTEM_CORRECTED 0x201L
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/*
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* EV5 Specific Machine Check logout frame for uncorrectable errors.
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* This is used to log uncorrectable errors such as double bit ECC errors.
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*
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* This typically resides in the cpu offset area of the logout frame.
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*/
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typedef struct {
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u_int64_t shadow[8]; /* Shadow reg. 8-14, 25 */
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u_int64_t paltemp[24]; /* PAL TEMP REGS. */
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u_int64_t exc_addr; /* Address of excepting ins. */
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u_int64_t exc_sum; /* Summary of arithmetic traps. */
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u_int64_t exc_mask; /* Exception mask. */
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u_int64_t pal_base; /* Base address for PALcode. */
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u_int64_t isr; /* Interrupt Status Reg. */
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u_int64_t icsr; /* CURRENT SETUP OF EV5 IBOX */
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u_int64_t ic_perr_stat; /*
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* I-CACHE Reg:
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* <13> IBOX Timeout
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* <12> TAG parity
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* <11> Data parity
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*/
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u_int64_t dc_perr_stat; /* D-CACHE error Reg:
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* Bits set to 1:
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* <2> Data error in bank 0
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* <3> Data error in bank 1
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* <4> Tag error in bank 0
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* <5> Tag error in bank 1
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*/
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u_int64_t va; /* Effective VA of fault or miss. */
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u_int64_t mm_stat; /*
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* Holds the reason for D-stream
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* fault or D-cache parity errors
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*/
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u_int64_t sc_addr; /*
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* Address that was being accessed
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* when EV5 detected Secondary cache
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* failure.
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*/
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u_int64_t sc_stat; /*
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* Helps determine if the error was
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* TAG/Data parity(Secondary Cache)
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*/
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u_int64_t bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */
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u_int64_t ei_addr; /*
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* Physical address of any transfer
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* that is logged in the EV5 EI_STAT
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*/
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u_int64_t fill_syndrome; /* For correcting ECC errors. */
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u_int64_t ei_stat; /*
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* Helps identify reason of any
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* processor uncorrectable error
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* at its external interface.
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*/
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u_int64_t ld_lock; /* Contents of EV5 LD_LOCK register*/
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} mc_uc_ev5;
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#define EV5_IC_PERR_IBOXTMO 0x2000
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/*
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* EV5 Specific Machine Check logout frame for correctable errors.
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*
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* This is used to log correctable errors such as Single bit ECC errors.
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*/
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typedef struct {
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u_int64_t ei_addr; /*
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* Physical address of any transfer
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* that is logged in the EV5 EI_STAT
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*/
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u_int64_t fill_syndrome; /* For correcting ECC errors. */
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u_int64_t ei_stat; /*
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* Helps identify reason of any
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* processor uncorrectable error
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* at its external interface.
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*/
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u_int64_t isr; /* Interrupt Status Reg. */
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} mc_cc_ev5;
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#ifdef _KERNEL
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extern void ev5_logout_print(mc_hdr_ev5 *, mc_uc_ev5 *);
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#endif
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