280 lines
8.2 KiB
C
280 lines
8.2 KiB
C
/* $NetBSD: cpu.h,v 1.19 1999/08/10 21:08:06 thorpej Exp $ */
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/*
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* cpu.h
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*
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* CPU specific symbols
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*
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* Created : 18/09/94
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*
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* Based on kate/katelib/arm6.h
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*/
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#ifndef _ARM32_CPU_H_
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#define _ARM32_CPU_H_
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#if defined(_KERNEL) && !defined(_LKM)
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#include "opt_cputypes.h"
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#endif
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#ifndef _LOCORE
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#include <machine/frame.h>
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#endif /* !_LOCORE */
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#include <machine/psl.h>
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#if defined(CPU_ARM7500) && !defined(CPU_ARM7)
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#error "option CPU_ARM7 is required with CPU_ARM7500"
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#endif
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#ifdef CPU_ARM7500
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#ifdef CPU_ARM6
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#error "CPU options CPU_ARM6 and CPU_ARM7500 are not compatible"
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#endif
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#ifdef CPU_ARM8
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#error "CPU options CPU_ARM8 and CPU_ARM7500 are not compatible"
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#endif
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#ifdef CPU_SA110
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#error "CPU options CPU_SA110 and CPU_ARM7500 are not compatible"
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#endif
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#endif /* CPU_ARM7500 */
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#define COPY_SIGCODE /* copy sigcode above user stack in exec */
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/*
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* ARM Process Status Register
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*
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* The picture in the ARM manuals looks like this:
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* 3 3 2 2 2
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* 1 0 9 8 7 8 7 6 5 4 0
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* +-------+---------------------------------------+-+-+-+---------+
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* | flags | reserved |I|F| |M M M M M|
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* |n z c v| | | | |4 3 2 1 0|
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* +-------+---------------------------------------+-+-+-+---------+
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*/
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#define PSR_FLAGS 0xf0000000 /* flags */
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#define PSR_N_bit (1 << 31) /* negative */
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#define PSR_Z_bit (1 << 30) /* zero */
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#define PSR_C_bit (1 << 29) /* carry */
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#define PSR_V_bit (1 << 28) /* overflow */
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#define I32_bit (1 << 7) /* IRQ disable */
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#define F32_bit (1 << 6) /* FIQ disable */
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#define PSR_MODE 0x0000001f /* mode mask */
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#define PSR_USR32_MODE 0x00000010
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#define PSR_FIQ32_MODE 0x00000011
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#define PSR_IRQ32_MODE 0x00000012
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#define PSR_SVC32_MODE 0x00000013
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#define PSR_ABT32_MODE 0x00000017
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#define PSR_UND32_MODE 0x0000001b
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#define PSR_32_MODE 0x00000010
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#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
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#define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE)
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/*
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* ARM Instructions
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*
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* 3 3 2 2 2
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* 1 0 9 8 7 0
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* +-------+-------------------------------------------------------+
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* | cond | instruction dependant |
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* |c c c c| |
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* +-------+-------------------------------------------------------+
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*/
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#define INSN_SIZE 4 /* Always 4 bytes */
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#define INSN_COND_MASK 0xf0000000 /* Condition mask */
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#define INSN_COND_AL 0xe0000000 /* Always condition */
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/* Some of the definitions below need cleaning up for V3/V4 architectures */
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#define CPU_ID_DESIGNER_MASK 0xff000000
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#define CPU_ID_ARM_LTD 0x41000000
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#define CPU_ID_DEC 0x44000000
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#define CPU_ID_TYPE_MASK 0x00ff0000
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#define CPU_ID_ARM 0x00560000
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#define CPU_ID_ARM7500 0x00020000
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#define CPU_ID_CPU_MASK 0x0000fff0
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#define ID_ARM610 0x00000610
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#define ID_ARM700 0x00007000
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#define ID_ARM710 0x00007100
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#define ID_ARM810 0x00008100
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#define ID_SA110 0x0000a100
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#define CPU_ID_REVISION_MASK 0x0000000f
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#define CPU_CONTROL_MMU_ENABLE 0x0001
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#define CPU_CONTROL_AFLT_ENABLE 0x0002
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#define CPU_CONTROL_DC_ENABLE 0x0004
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#define CPU_CONTROL_WBUF_ENABLE 0x0008
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#define CPU_CONTROL_32BP_ENABLE 0x0010
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#define CPU_CONTROL_32BD_ENABLE 0x0020
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#define CPU_CONTROL_LABT_ENABLE 0x0040
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#define CPU_CONTROL_BEND_ENABLE 0x0080
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#define CPU_CONTROL_SYST_ENABLE 0x0100
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#define CPU_CONTROL_ROM_ENABLE 0x0200
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#define CPU_CONTROL_CPCLK 0x0400
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#define CPU_CONTROL_BPRD_ENABLE 0x0800
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#define CPU_CONTROL_IC_ENABLE 0x1000
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#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
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/* Fault status register definitions */
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#define FAULT_TYPE_MASK 0x0f
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#define FAULT_USER 0x10
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#define FAULT_WRTBUF_0 0x00
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#define FAULT_WRTBUF_1 0x02
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#define FAULT_BUSERR_0 0x04
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#define FAULT_BUSERR_1 0x06
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#define FAULT_BUSERR_2 0x08
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#define FAULT_BUSERR_3 0x0a
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#define FAULT_ALIGN_0 0x01
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#define FAULT_ALIGN_1 0x03
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#define FAULT_BUSTRNL1 0x0c
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#define FAULT_BUSTRNL2 0x0e
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#define FAULT_TRANS_S 0x05
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#define FAULT_TRANS_P 0x07
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#define FAULT_DOMAIN_S 0x09
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#define FAULT_DOMAIN_P 0x0b
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#define FAULT_PERM_S 0x0d
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#define FAULT_PERM_P 0x0f
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#ifdef _LOCORE
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#define IRQdisable \
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stmfd sp!, {r0} ; \
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mrs r0, cpsr_all ; \
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orr r0, r0, #(I32_bit) ; \
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msr cpsr_all, r0 ; \
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ldmfd sp!, {r0}
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#define IRQenable \
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stmfd sp!, {r0} ; \
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mrs r0, cpsr_all ; \
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bic r0, r0, #(I32_bit) ; \
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msr cpsr_all, r0 ; \
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ldmfd sp!, {r0}
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#else
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#define IRQdisable SetCPSR(I32_bit, I32_bit);
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#define IRQenable SetCPSR(I32_bit, 0);
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#endif /* _LOCORE */
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/*
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* Return TRUE/FALSE (1/0) depending on whether the frame came from USR
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* mode or not.
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*/
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#define CLKF_USERMODE(frame) ((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE)
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/*
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* This needs straighening, prob is the frame does not have info on the priority
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* a guess that needs trying is (current_spl_level == SPL0)
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*/
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#define CLKF_BASEPRI(frame) ((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE)
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#define CLKF_PC(frame) (frame->if_pc)
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/*#define CLKF_INTR(frame) (current_intr_depth > 1)*/
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/* Hack to treat FPE time as interrupt time so we can measure it */
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#define CLKF_INTR(frame) ((current_intr_depth > 1) || (frame->if_spsr & PSR_MODE) == PSR_UND32_MODE)
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_wait(p) /* nothing */
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#define cpu_number() 0
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) setsoftast()
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#if defined(_KERNEL) && !defined(_LOCORE)
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extern int current_intr_depth;
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/* stubs.c */
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void need_resched __P((void));
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void need_proftick __P((struct proc *p));
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/* locore.S */
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void atomic_set_bit __P((u_int *address, u_int setmask));
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void atomic_clear_bit __P((u_int *address, u_int clearmask));
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/* cpuswitch.S */
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struct pcb;
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void savectx __P((struct pcb *pcb));
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/* ast.c */
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void userret __P((register struct proc *p, int pc, u_quad_t oticks));
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/* machdep.h */
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void bootsync __P((void));
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/* strstr.c */
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char *strstr __P((const char *s1, const char *s2));
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/* syscall.c */
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void child_return __P((void *));
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#endif /* _KERNEL && !_LOCORE */
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_DEBUG 1 /* int: misc kernel debug control */
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#define CPU_MAXID 2 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "debug", CTLTYPE_INT }, \
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}
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#endif /* !_ARM32_CPU_H_ */
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/* End of cpu.h */
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