1472 lines
42 KiB
C
1472 lines
42 KiB
C
/* $NetBSD: pci_subr.c,v 1.87 2011/06/06 18:27:12 msaitoh Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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* Copyright (c) 1995, 1996, 1998, 2000
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* Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI autoconfiguration support functions.
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*
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* Note: This file is also built into a userland library (libpci).
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* Pay attention to this when you make modifications.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.87 2011/06/06 18:27:12 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_pci.h"
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#endif
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#include <sys/param.h>
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#ifdef _KERNEL
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#include <sys/systm.h>
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#include <sys/intr.h>
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#include <sys/module.h>
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#else
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#include <pci.h>
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#include <stdbool.h>
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#include <stdio.h>
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#endif
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#include <dev/pci/pcireg.h>
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#ifdef _KERNEL
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#include <dev/pci/pcivar.h>
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#endif
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/*
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* Descriptions of known PCI classes and subclasses.
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*
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* Subclasses are described in the same way as classes, but have a
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* NULL subclass pointer.
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*/
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struct pci_class {
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const char *name;
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int val; /* as wide as pci_{,sub}class_t */
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const struct pci_class *subclasses;
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};
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static const struct pci_class pci_subclass_prehistoric[] = {
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{ "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, },
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{ "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_mass_storage[] = {
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{ "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, },
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{ "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, },
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{ "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, },
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{ "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, },
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{ "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, },
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{ "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, },
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{ "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, },
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{ "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_network[] = {
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{ "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, },
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{ "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, },
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{ "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, },
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{ "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, },
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{ "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, },
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{ "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, },
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{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_display[] = {
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{ "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, },
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{ "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, },
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{ "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_multimedia[] = {
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{ "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
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{ "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
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{ "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
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{ "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_memory[] = {
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{ "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, },
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{ "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_bridge[] = {
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{ "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, },
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{ "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, },
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{ "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, },
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{ "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, },
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{ "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, },
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{ "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, },
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{ "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, },
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{ "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, },
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{ "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, },
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{ "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, },
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{ "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_communications[] = {
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{ "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, },
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{ "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, },
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{ "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, },
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{ "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, },
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{ "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, },
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{ "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_system[] = {
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{ "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, },
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{ "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, },
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{ "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, },
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{ "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, },
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{ "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, },
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{ "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_input[] = {
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{ "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, },
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{ "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, },
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{ "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, },
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{ "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, },
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{ "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_dock[] = {
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{ "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_processor[] = {
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{ "386", PCI_SUBCLASS_PROCESSOR_386, NULL, },
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{ "486", PCI_SUBCLASS_PROCESSOR_486, NULL, },
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{ "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, },
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{ "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, },
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{ "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, },
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{ "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, },
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{ "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_serialbus[] = {
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{ "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, },
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{ "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, },
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{ "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, },
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{ "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, },
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/* XXX Fiber Channel/_FIBRECHANNEL */
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{ "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, },
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{ "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, },
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{ "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,},
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{ "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, },
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{ "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, },
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{ "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_wireless[] = {
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{ "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, },
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{ "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, },
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{ "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, },
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{ "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, },
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{ "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, },
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{ "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, },
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{ "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_i2o[] = {
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{ "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_satcom[] = {
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{ "TV", PCI_SUBCLASS_SATCOM_TV, NULL, },
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{ "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, },
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{ "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, },
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{ "data", PCI_SUBCLASS_SATCOM_DATA, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_crypto[] = {
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{ "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, },
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{ "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,},
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{ "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_subclass_dasp[] = {
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{ "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, },
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{ "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, },
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{ "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, },
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{ "management", PCI_SUBCLASS_DASP_MGMT, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, },
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{ NULL, 0, NULL, },
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};
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static const struct pci_class pci_class[] = {
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{ "prehistoric", PCI_CLASS_PREHISTORIC,
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pci_subclass_prehistoric, },
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{ "mass storage", PCI_CLASS_MASS_STORAGE,
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pci_subclass_mass_storage, },
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{ "network", PCI_CLASS_NETWORK,
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pci_subclass_network, },
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{ "display", PCI_CLASS_DISPLAY,
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pci_subclass_display, },
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{ "multimedia", PCI_CLASS_MULTIMEDIA,
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pci_subclass_multimedia, },
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{ "memory", PCI_CLASS_MEMORY,
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pci_subclass_memory, },
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{ "bridge", PCI_CLASS_BRIDGE,
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pci_subclass_bridge, },
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{ "communications", PCI_CLASS_COMMUNICATIONS,
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pci_subclass_communications, },
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{ "system", PCI_CLASS_SYSTEM,
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pci_subclass_system, },
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{ "input", PCI_CLASS_INPUT,
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pci_subclass_input, },
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{ "dock", PCI_CLASS_DOCK,
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pci_subclass_dock, },
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{ "processor", PCI_CLASS_PROCESSOR,
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pci_subclass_processor, },
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{ "serial bus", PCI_CLASS_SERIALBUS,
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pci_subclass_serialbus, },
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{ "wireless", PCI_CLASS_WIRELESS,
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pci_subclass_wireless, },
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{ "I2O", PCI_CLASS_I2O,
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pci_subclass_i2o, },
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{ "satellite comm", PCI_CLASS_SATCOM,
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pci_subclass_satcom, },
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{ "crypto", PCI_CLASS_CRYPTO,
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pci_subclass_crypto, },
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{ "DASP", PCI_CLASS_DASP,
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pci_subclass_dasp, },
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{ "undefined", PCI_CLASS_UNDEFINED,
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NULL, },
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{ NULL, 0,
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NULL, },
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};
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void pci_load_verbose(void);
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#if defined(_KERNEL)
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/*
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* In kernel, these routines are provided and linked via the
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* pciverbose module.
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*/
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const char *pci_findvendor_stub(pcireg_t);
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const char *pci_findproduct_stub(pcireg_t);
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const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub;
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const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub;
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const char *pci_unmatched = "";
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#else
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/*
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* For userland we just set the vectors here.
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*/
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const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real;
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const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real;
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const char *pci_unmatched = "unmatched ";
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#endif
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int pciverbose_loaded = 0;
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#if defined(_KERNEL)
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/*
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* Routine to load the pciverbose kernel module as needed
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*/
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void pci_load_verbose(void)
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{
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if (pciverbose_loaded == 0)
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module_autoload("pciverbose", MODULE_CLASS_MISC);
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}
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const char *pci_findvendor_stub(pcireg_t id_reg)
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{
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pci_load_verbose();
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if (pciverbose_loaded)
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return pci_findvendor(id_reg);
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else
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return NULL;
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}
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const char *pci_findproduct_stub(pcireg_t id_reg)
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{
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pci_load_verbose();
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if (pciverbose_loaded)
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return pci_findproduct(id_reg);
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else
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return NULL;
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}
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#endif
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void
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pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp,
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size_t l)
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{
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pci_vendor_id_t vendor;
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pci_product_id_t product;
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pci_class_t class;
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pci_subclass_t subclass;
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pci_interface_t interface;
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pci_revision_t revision;
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const char *unmatched = pci_unmatched;
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const char *vendor_namep, *product_namep;
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const struct pci_class *classp, *subclassp;
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char *ep;
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ep = cp + l;
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vendor = PCI_VENDOR(id_reg);
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product = PCI_PRODUCT(id_reg);
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class = PCI_CLASS(class_reg);
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subclass = PCI_SUBCLASS(class_reg);
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interface = PCI_INTERFACE(class_reg);
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revision = PCI_REVISION(class_reg);
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vendor_namep = pci_findvendor(id_reg);
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product_namep = pci_findproduct(id_reg);
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classp = pci_class;
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while (classp->name != NULL) {
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if (class == classp->val)
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break;
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classp++;
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}
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subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
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while (subclassp && subclassp->name != NULL) {
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if (subclass == subclassp->val)
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break;
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subclassp++;
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}
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if (vendor_namep == NULL)
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cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x",
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unmatched, vendor, product);
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else if (product_namep != NULL)
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cp += snprintf(cp, ep - cp, "%s %s", vendor_namep,
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product_namep);
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else
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cp += snprintf(cp, ep - cp, "%s product 0x%04x",
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vendor_namep, product);
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if (showclass) {
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cp += snprintf(cp, ep - cp, " (");
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if (classp->name == NULL)
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cp += snprintf(cp, ep - cp,
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"class 0x%02x, subclass 0x%02x", class, subclass);
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else {
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if (subclassp == NULL || subclassp->name == NULL)
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cp += snprintf(cp, ep - cp,
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"%s, subclass 0x%02x",
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classp->name, subclass);
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else
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cp += snprintf(cp, ep - cp, "%s %s",
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subclassp->name, classp->name);
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}
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if (interface != 0)
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cp += snprintf(cp, ep - cp, ", interface 0x%02x",
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interface);
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if (revision != 0)
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cp += snprintf(cp, ep - cp, ", revision 0x%02x",
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revision);
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cp += snprintf(cp, ep - cp, ")");
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}
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}
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/*
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* Print out most of the PCI configuration registers. Typically used
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* in a device attach routine like this:
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*
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* #ifdef MYDEV_DEBUG
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* printf("%s: ", device_xname(&sc->sc_dev));
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* pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
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* #endif
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*/
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|
|
#define i2o(i) ((i) * 4)
|
|
#define o2i(o) ((o) / 4)
|
|
#define onoff2(str, bit, onstr, offstr) \
|
|
printf(" %s: %s\n", (str), (rval & (bit)) ? onstr : offstr);
|
|
#define onoff(str, bit) onoff2(str, bit, "on", "off")
|
|
|
|
static void
|
|
pci_conf_print_common(
|
|
#ifdef _KERNEL
|
|
pci_chipset_tag_t pc, pcitag_t tag,
|
|
#endif
|
|
const pcireg_t *regs)
|
|
{
|
|
const char *name;
|
|
const struct pci_class *classp, *subclassp;
|
|
pcireg_t rval;
|
|
|
|
rval = regs[o2i(PCI_ID_REG)];
|
|
name = pci_findvendor(rval);
|
|
if (name)
|
|
printf(" Vendor Name: %s (0x%04x)\n", name,
|
|
PCI_VENDOR(rval));
|
|
else
|
|
printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval));
|
|
name = pci_findproduct(rval);
|
|
if (name)
|
|
printf(" Device Name: %s (0x%04x)\n", name,
|
|
PCI_PRODUCT(rval));
|
|
else
|
|
printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval));
|
|
|
|
rval = regs[o2i(PCI_COMMAND_STATUS_REG)];
|
|
|
|
printf(" Command register: 0x%04x\n", rval & 0xffff);
|
|
onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE);
|
|
onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE);
|
|
onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE);
|
|
onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE);
|
|
onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE);
|
|
onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE);
|
|
onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE);
|
|
onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE);
|
|
onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE);
|
|
onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE);
|
|
onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE);
|
|
|
|
printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff);
|
|
onoff2("Interrupt status", PCI_STATUS_INT_STATUS, "active", "inactive");
|
|
onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT);
|
|
onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT);
|
|
onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT);
|
|
onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT);
|
|
onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR);
|
|
|
|
printf(" DEVSEL timing: ");
|
|
switch (rval & PCI_STATUS_DEVSEL_MASK) {
|
|
case PCI_STATUS_DEVSEL_FAST:
|
|
printf("fast");
|
|
break;
|
|
case PCI_STATUS_DEVSEL_MEDIUM:
|
|
printf("medium");
|
|
break;
|
|
case PCI_STATUS_DEVSEL_SLOW:
|
|
printf("slow");
|
|
break;
|
|
default:
|
|
printf("unknown/reserved"); /* XXX */
|
|
break;
|
|
}
|
|
printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25);
|
|
|
|
onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT);
|
|
onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT);
|
|
onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT);
|
|
onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR);
|
|
onoff("Parity error detected", PCI_STATUS_PARITY_DETECT);
|
|
|
|
rval = regs[o2i(PCI_CLASS_REG)];
|
|
for (classp = pci_class; classp->name != NULL; classp++) {
|
|
if (PCI_CLASS(rval) == classp->val)
|
|
break;
|
|
}
|
|
subclassp = (classp->name != NULL) ? classp->subclasses : NULL;
|
|
while (subclassp && subclassp->name != NULL) {
|
|
if (PCI_SUBCLASS(rval) == subclassp->val)
|
|
break;
|
|
subclassp++;
|
|
}
|
|
if (classp->name != NULL) {
|
|
printf(" Class Name: %s (0x%02x)\n", classp->name,
|
|
PCI_CLASS(rval));
|
|
if (subclassp != NULL && subclassp->name != NULL)
|
|
printf(" Subclass Name: %s (0x%02x)\n",
|
|
subclassp->name, PCI_SUBCLASS(rval));
|
|
else
|
|
printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
|
|
} else {
|
|
printf(" Class ID: 0x%02x\n", PCI_CLASS(rval));
|
|
printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
|
|
}
|
|
printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval));
|
|
printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval));
|
|
|
|
rval = regs[o2i(PCI_BHLC_REG)];
|
|
printf(" BIST: 0x%02x\n", PCI_BIST(rval));
|
|
printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval),
|
|
PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "",
|
|
PCI_HDRTYPE(rval));
|
|
printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval));
|
|
printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval));
|
|
}
|
|
|
|
static int
|
|
pci_conf_print_bar(
|
|
#ifdef _KERNEL
|
|
pci_chipset_tag_t pc, pcitag_t tag,
|
|
#endif
|
|
const pcireg_t *regs, int reg, const char *name
|
|
#ifdef _KERNEL
|
|
, int sizebar
|
|
#endif
|
|
)
|
|
{
|
|
int width;
|
|
pcireg_t rval, rval64h;
|
|
#ifdef _KERNEL
|
|
int s;
|
|
pcireg_t mask, mask64h;
|
|
#endif
|
|
|
|
width = 4;
|
|
|
|
/*
|
|
* Section 6.2.5.1, `Address Maps', tells us that:
|
|
*
|
|
* 1) The builtin software should have already mapped the
|
|
* device in a reasonable way.
|
|
*
|
|
* 2) A device which wants 2^n bytes of memory will hardwire
|
|
* the bottom n bits of the address to 0. As recommended,
|
|
* we write all 1s and see what we get back.
|
|
*/
|
|
|
|
rval = regs[o2i(reg)];
|
|
if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
|
|
PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
|
|
rval64h = regs[o2i(reg + 4)];
|
|
width = 8;
|
|
} else
|
|
rval64h = 0;
|
|
|
|
#ifdef _KERNEL
|
|
/* XXX don't size unknown memory type? */
|
|
if (rval != 0 && sizebar) {
|
|
/*
|
|
* The following sequence seems to make some devices
|
|
* (e.g. host bus bridges, which don't normally
|
|
* have their space mapped) very unhappy, to
|
|
* the point of crashing the system.
|
|
*
|
|
* Therefore, if the mapping register is zero to
|
|
* start out with, don't bother trying.
|
|
*/
|
|
s = splhigh();
|
|
pci_conf_write(pc, tag, reg, 0xffffffff);
|
|
mask = pci_conf_read(pc, tag, reg);
|
|
pci_conf_write(pc, tag, reg, rval);
|
|
if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM &&
|
|
PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) {
|
|
pci_conf_write(pc, tag, reg + 4, 0xffffffff);
|
|
mask64h = pci_conf_read(pc, tag, reg + 4);
|
|
pci_conf_write(pc, tag, reg + 4, rval64h);
|
|
} else
|
|
mask64h = 0;
|
|
splx(s);
|
|
} else
|
|
mask = mask64h = 0;
|
|
#endif /* _KERNEL */
|
|
|
|
printf(" Base address register at 0x%02x", reg);
|
|
if (name)
|
|
printf(" (%s)", name);
|
|
printf("\n ");
|
|
if (rval == 0) {
|
|
printf("not implemented(?)\n");
|
|
return width;
|
|
}
|
|
printf("type: ");
|
|
if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) {
|
|
const char *type, *prefetch;
|
|
|
|
switch (PCI_MAPREG_MEM_TYPE(rval)) {
|
|
case PCI_MAPREG_MEM_TYPE_32BIT:
|
|
type = "32-bit";
|
|
break;
|
|
case PCI_MAPREG_MEM_TYPE_32BIT_1M:
|
|
type = "32-bit-1M";
|
|
break;
|
|
case PCI_MAPREG_MEM_TYPE_64BIT:
|
|
type = "64-bit";
|
|
break;
|
|
default:
|
|
type = "unknown (XXX)";
|
|
break;
|
|
}
|
|
if (PCI_MAPREG_MEM_PREFETCHABLE(rval))
|
|
prefetch = "";
|
|
else
|
|
prefetch = "non";
|
|
printf("%s %sprefetchable memory\n", type, prefetch);
|
|
switch (PCI_MAPREG_MEM_TYPE(rval)) {
|
|
case PCI_MAPREG_MEM_TYPE_64BIT:
|
|
printf(" base: 0x%016llx, ",
|
|
PCI_MAPREG_MEM64_ADDR(
|
|
((((long long) rval64h) << 32) | rval)));
|
|
#ifdef _KERNEL
|
|
if (sizebar)
|
|
printf("size: 0x%016llx",
|
|
PCI_MAPREG_MEM64_SIZE(
|
|
((((long long) mask64h) << 32) | mask)));
|
|
else
|
|
#endif /* _KERNEL */
|
|
printf("not sized");
|
|
printf("\n");
|
|
break;
|
|
case PCI_MAPREG_MEM_TYPE_32BIT:
|
|
case PCI_MAPREG_MEM_TYPE_32BIT_1M:
|
|
default:
|
|
printf(" base: 0x%08x, ",
|
|
PCI_MAPREG_MEM_ADDR(rval));
|
|
#ifdef _KERNEL
|
|
if (sizebar)
|
|
printf("size: 0x%08x",
|
|
PCI_MAPREG_MEM_SIZE(mask));
|
|
else
|
|
#endif /* _KERNEL */
|
|
printf("not sized");
|
|
printf("\n");
|
|
break;
|
|
}
|
|
} else {
|
|
#ifdef _KERNEL
|
|
if (sizebar)
|
|
printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16);
|
|
#endif /* _KERNEL */
|
|
printf("i/o\n");
|
|
printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval));
|
|
#ifdef _KERNEL
|
|
if (sizebar)
|
|
printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask));
|
|
else
|
|
#endif /* _KERNEL */
|
|
printf("not sized");
|
|
printf("\n");
|
|
}
|
|
|
|
return width;
|
|
}
|
|
|
|
static void
|
|
pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast)
|
|
{
|
|
int off, needaddr, neednl;
|
|
|
|
needaddr = 1;
|
|
neednl = 0;
|
|
for (off = first; off < pastlast; off += 4) {
|
|
if ((off % 16) == 0 || needaddr) {
|
|
printf(" 0x%02x:", off);
|
|
needaddr = 0;
|
|
}
|
|
printf(" 0x%08x", regs[o2i(off)]);
|
|
neednl = 1;
|
|
if ((off % 16) == 12) {
|
|
printf("\n");
|
|
neednl = 0;
|
|
}
|
|
}
|
|
if (neednl)
|
|
printf("\n");
|
|
}
|
|
|
|
static void
|
|
pci_conf_print_type0(
|
|
#ifdef _KERNEL
|
|
pci_chipset_tag_t pc, pcitag_t tag,
|
|
#endif
|
|
const pcireg_t *regs
|
|
#ifdef _KERNEL
|
|
, int sizebars
|
|
#endif
|
|
)
|
|
{
|
|
int off, width;
|
|
pcireg_t rval;
|
|
|
|
for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
|
|
#ifdef _KERNEL
|
|
width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
|
|
#else
|
|
width = pci_conf_print_bar(regs, off, NULL);
|
|
#endif
|
|
}
|
|
|
|
printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]);
|
|
|
|
rval = regs[o2i(PCI_SUBSYS_ID_REG)];
|
|
printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
|
|
printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
|
|
|
|
/* XXX */
|
|
printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]);
|
|
|
|
if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
|
|
printf(" Capability list pointer: 0x%02x\n",
|
|
PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
|
|
else
|
|
printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
|
|
|
|
printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
|
|
|
|
rval = regs[o2i(PCI_INTERRUPT_REG)];
|
|
printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff);
|
|
printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff);
|
|
printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
|
|
switch (PCI_INTERRUPT_PIN(rval)) {
|
|
case PCI_INTERRUPT_PIN_NONE:
|
|
printf("(none)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_A:
|
|
printf("(pin A)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_B:
|
|
printf("(pin B)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_C:
|
|
printf("(pin C)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_D:
|
|
printf("(pin D)");
|
|
break;
|
|
default:
|
|
printf("(? ? ?)");
|
|
break;
|
|
}
|
|
printf("\n");
|
|
printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
|
|
}
|
|
|
|
static void
|
|
pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
|
|
{
|
|
bool check_slot = false;
|
|
|
|
printf("\n PCI Express Capabilities Register\n");
|
|
printf(" Capability version: %x\n",
|
|
(unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16));
|
|
printf(" Device type: ");
|
|
switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) {
|
|
case 0x0:
|
|
printf("PCI Express Endpoint device\n");
|
|
break;
|
|
case 0x1:
|
|
printf("Legacy PCI Express Endpoint device\n");
|
|
break;
|
|
case 0x4:
|
|
printf("Root Port of PCI Express Root Complex\n");
|
|
check_slot = true;
|
|
break;
|
|
case 0x5:
|
|
printf("Upstream Port of PCI Express Switch\n");
|
|
break;
|
|
case 0x6:
|
|
printf("Downstream Port of PCI Express Switch\n");
|
|
check_slot = true;
|
|
break;
|
|
case 0x7:
|
|
printf("PCI Express to PCI/PCI-X Bridge\n");
|
|
break;
|
|
case 0x8:
|
|
printf("PCI/PCI-X to PCI Express Bridge\n");
|
|
break;
|
|
default:
|
|
printf("unknown\n");
|
|
break;
|
|
}
|
|
if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0)
|
|
printf(" Slot implemented\n");
|
|
printf(" Interrupt Message Number: %x\n",
|
|
(unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27));
|
|
printf(" Link Capabilities Register: 0x%08x\n",
|
|
regs[o2i(capoff + 0x0c)]);
|
|
printf(" Maximum Link Speed: ");
|
|
if ((regs[o2i(capoff + 0x0c)] & 0x000f) != 1) {
|
|
printf("unknown %u value\n",
|
|
(regs[o2i(capoff + 0x0c)] & 0x000f));
|
|
} else {
|
|
printf("2.5Gb/s\n");
|
|
}
|
|
printf(" Maximum Link Width: x%u lanes\n",
|
|
(regs[o2i(capoff + 0x0c)] & 0x03f0) >> 4);
|
|
printf(" Port Number: %u\n", regs[o2i(capoff + 0x0c)] >> 24);
|
|
printf(" Link Status Register: 0x%04x\n",
|
|
regs[o2i(capoff + 0x10)] >> 16);
|
|
printf(" Negotiated Link Speed: ");
|
|
if (((regs[o2i(capoff + 0x10)] >> 16) & 0x000f) != 1) {
|
|
printf("unknown %u value\n",
|
|
(regs[o2i(capoff + 0x10)] >> 16) & 0x000f);
|
|
} else {
|
|
printf("2.5Gb/s\n");
|
|
}
|
|
printf(" Negotiated Link Width: x%u lanes\n",
|
|
(regs[o2i(capoff + 0x10)] >> 20) & 0x003f);
|
|
if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) {
|
|
printf(" Slot Control Register:\n");
|
|
if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0)
|
|
printf(" Attention Button Pressed Enabled\n");
|
|
if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0)
|
|
printf(" Power Fault Detected Enabled\n");
|
|
if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0)
|
|
printf(" MRL Sensor Changed Enabled\n");
|
|
if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0)
|
|
printf(" Presense Detected Changed Enabled\n");
|
|
if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0)
|
|
printf(" Command Completed Interrupt Enabled\n");
|
|
if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0)
|
|
printf(" Hot-Plug Interrupt Enabled\n");
|
|
printf(" Attention Indicator Control: ");
|
|
switch ((regs[o2i(capoff + 0x18)] & 0x00c0) >> 6) {
|
|
case 0x0:
|
|
printf("reserved\n");
|
|
break;
|
|
case 0x1:
|
|
printf("on\n");
|
|
break;
|
|
case 0x2:
|
|
printf("blink\n");
|
|
break;
|
|
case 0x3:
|
|
printf("off\n");
|
|
break;
|
|
}
|
|
printf(" Power Indicator Control: ");
|
|
switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) {
|
|
case 0x0:
|
|
printf("reserved\n");
|
|
break;
|
|
case 0x1:
|
|
printf("on\n");
|
|
break;
|
|
case 0x2:
|
|
printf("blink\n");
|
|
break;
|
|
case 0x3:
|
|
printf("off\n");
|
|
break;
|
|
}
|
|
printf(" Power Controller Control: ");
|
|
if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0)
|
|
printf("off\n");
|
|
else
|
|
printf("on\n");
|
|
}
|
|
}
|
|
|
|
static const char *
|
|
pci_conf_print_pcipm_cap_aux(uint16_t caps)
|
|
{
|
|
switch ((caps >> 6) & 7) {
|
|
case 0: return "self-powered";
|
|
case 1: return "55 mA";
|
|
case 2: return "100 mA";
|
|
case 3: return "160 mA";
|
|
case 4: return "220 mA";
|
|
case 5: return "270 mA";
|
|
case 6: return "320 mA";
|
|
case 7:
|
|
default: return "375 mA";
|
|
}
|
|
}
|
|
|
|
static const char *
|
|
pci_conf_print_pcipm_cap_pmrev(uint8_t val)
|
|
{
|
|
static const char unk[] = "unknown";
|
|
static const char *pmrev[8] = {
|
|
unk, "1.0", "1.1", "1.2", unk, unk, unk, unk
|
|
};
|
|
if (val > 7)
|
|
return unk;
|
|
return pmrev[val];
|
|
}
|
|
|
|
static void
|
|
pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
|
|
{
|
|
uint16_t caps, pmcsr;
|
|
|
|
caps = regs[o2i(capoff)] >> 16;
|
|
pmcsr = regs[o2i(capoff + 0x04)] & 0xffff;
|
|
|
|
printf("\n PCI Power Management Capabilities Register\n");
|
|
|
|
printf(" Capabilities register: 0x%04x\n", caps);
|
|
printf(" Version: %s\n",
|
|
pci_conf_print_pcipm_cap_pmrev(caps & 0x3));
|
|
printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off");
|
|
printf(" Device specific initialization: %s\n",
|
|
caps & 0x20 ? "on" : "off");
|
|
printf(" 3.3V auxiliary current: %s\n",
|
|
pci_conf_print_pcipm_cap_aux(caps));
|
|
printf(" D1 power management state support: %s\n",
|
|
(caps >> 9) & 1 ? "on" : "off");
|
|
printf(" D2 power management state support: %s\n",
|
|
(caps >> 10) & 1 ? "on" : "off");
|
|
printf(" PME# support: 0x%02x\n", caps >> 11);
|
|
|
|
printf(" Control/status register: 0x%04x\n", pmcsr);
|
|
printf(" Power state: D%d\n", pmcsr & 3);
|
|
printf(" PCI Express reserved: %s\n",
|
|
(pmcsr >> 2) & 1 ? "on" : "off");
|
|
printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off");
|
|
printf(" PME# assertion %sabled\n",
|
|
(pmcsr >> 8) & 1 ? "en" : "dis");
|
|
printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off");
|
|
}
|
|
|
|
static void
|
|
pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
|
|
{
|
|
uint32_t ctl, mmc, mme;
|
|
|
|
regs += o2i(capoff);
|
|
ctl = *regs++;
|
|
mmc = (ctl >> PCI_MSI_CTL_MMC_SHIFT) & PCI_MSI_CTL_MMC_MASK;
|
|
mme = (ctl >> PCI_MSI_CTL_MME_SHIFT) & PCI_MSI_CTL_MME_MASK;
|
|
|
|
printf("\n PCI Message Signaled Interrupt\n");
|
|
|
|
printf(" Message Control register: 0x%04x\n", ctl >> 16);
|
|
printf(" MSI Enabled: %s\n",
|
|
ctl & PCI_MSI_CTL_MSI_ENABLE ? "yes" : "no");
|
|
printf(" Multiple Message Capable: %s (%d vector%s)\n",
|
|
mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : "");
|
|
printf(" Multiple Message Enabled: %s (%d vector%s)\n",
|
|
mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : "");
|
|
printf(" 64 Bit Address Capable: %s\n",
|
|
ctl & PCI_MSI_CTL_64BIT_ADDR ? "yes" : "no");
|
|
printf(" Per-Vector Masking Capable: %s\n",
|
|
ctl & PCI_MSI_CTL_PERVEC_MASK ? "yes" : "no");
|
|
printf(" Message Address %sregister: 0x%08x\n",
|
|
ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
|
|
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
|
|
printf(" Message Address %sregister: 0x%08x\n",
|
|
"(upper) ", *regs++);
|
|
}
|
|
printf(" Message Data register: 0x%08x\n", *regs++);
|
|
if (ctl & PCI_MSI_CTL_PERVEC_MASK) {
|
|
printf(" Vector Mask register: 0x%08x\n", *regs++);
|
|
printf(" Vector Pending register: 0x%08x\n", *regs++);
|
|
}
|
|
}
|
|
static void
|
|
pci_conf_print_caplist(
|
|
#ifdef _KERNEL
|
|
pci_chipset_tag_t pc, pcitag_t tag,
|
|
#endif
|
|
const pcireg_t *regs, int capoff)
|
|
{
|
|
int off;
|
|
pcireg_t rval;
|
|
int pcie_off = -1, pcipm_off = -1, msi_off = -1;
|
|
|
|
for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
|
|
off != 0;
|
|
off = PCI_CAPLIST_NEXT(regs[o2i(off)])) {
|
|
rval = regs[o2i(off)];
|
|
printf(" Capability register at 0x%02x\n", off);
|
|
|
|
printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval));
|
|
switch (PCI_CAPLIST_CAP(rval)) {
|
|
case PCI_CAP_RESERVED0:
|
|
printf("reserved");
|
|
break;
|
|
case PCI_CAP_PWRMGMT:
|
|
printf("Power Management, rev. %s",
|
|
pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07));
|
|
pcipm_off = off;
|
|
break;
|
|
case PCI_CAP_AGP:
|
|
printf("AGP, rev. %d.%d",
|
|
PCI_CAP_AGP_MAJOR(rval),
|
|
PCI_CAP_AGP_MINOR(rval));
|
|
break;
|
|
case PCI_CAP_VPD:
|
|
printf("VPD");
|
|
break;
|
|
case PCI_CAP_SLOTID:
|
|
printf("SlotID");
|
|
break;
|
|
case PCI_CAP_MSI:
|
|
printf("MSI");
|
|
msi_off = off;
|
|
break;
|
|
case PCI_CAP_CPCI_HOTSWAP:
|
|
printf("CompactPCI Hot-swapping");
|
|
break;
|
|
case PCI_CAP_PCIX:
|
|
printf("PCI-X");
|
|
break;
|
|
case PCI_CAP_LDT:
|
|
printf("LDT");
|
|
break;
|
|
case PCI_CAP_VENDSPEC:
|
|
printf("Vendor-specific");
|
|
break;
|
|
case PCI_CAP_DEBUGPORT:
|
|
printf("Debug Port");
|
|
break;
|
|
case PCI_CAP_CPCI_RSRCCTL:
|
|
printf("CompactPCI Resource Control");
|
|
break;
|
|
case PCI_CAP_HOTPLUG:
|
|
printf("Hot-Plug");
|
|
break;
|
|
case PCI_CAP_AGP8:
|
|
printf("AGP 8x");
|
|
break;
|
|
case PCI_CAP_SECURE:
|
|
printf("Secure Device");
|
|
break;
|
|
case PCI_CAP_PCIEXPRESS:
|
|
printf("PCI Express");
|
|
pcie_off = off;
|
|
break;
|
|
case PCI_CAP_MSIX:
|
|
printf("MSI-X");
|
|
break;
|
|
case PCI_CAP_SATA:
|
|
printf("SATA");
|
|
break;
|
|
case PCI_CAP_PCIAF:
|
|
printf("Advanced Features");
|
|
break;
|
|
default:
|
|
printf("unknown");
|
|
}
|
|
printf(")\n");
|
|
}
|
|
if (msi_off != -1)
|
|
pci_conf_print_msi_cap(regs, msi_off);
|
|
if (pcipm_off != -1)
|
|
pci_conf_print_pcipm_cap(regs, pcipm_off);
|
|
if (pcie_off != -1)
|
|
pci_conf_print_pcie_cap(regs, pcie_off);
|
|
}
|
|
|
|
/* Print the Secondary Status Register. */
|
|
static void
|
|
pci_conf_print_ssr(pcireg_t rval)
|
|
{
|
|
pcireg_t devsel;
|
|
|
|
printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */
|
|
onoff("66 MHz capable", __BIT(5));
|
|
onoff("User Definable Features (UDF) support", __BIT(6));
|
|
onoff("Fast back-to-back capable", __BIT(7));
|
|
onoff("Data parity error detected", __BIT(8));
|
|
|
|
printf(" DEVSEL timing: ");
|
|
devsel = __SHIFTOUT(rval, __BITS(10, 9));
|
|
switch (devsel) {
|
|
case 0:
|
|
printf("fast");
|
|
break;
|
|
case 1:
|
|
printf("medium");
|
|
break;
|
|
case 2:
|
|
printf("slow");
|
|
break;
|
|
default:
|
|
printf("unknown/reserved"); /* XXX */
|
|
break;
|
|
}
|
|
printf(" (0x%x)\n", devsel);
|
|
|
|
onoff("Signalled target abort", __BIT(11));
|
|
onoff("Received target abort", __BIT(12));
|
|
onoff("Received master abort", __BIT(13));
|
|
onoff("Received system error", __BIT(14));
|
|
onoff("Detected parity error", __BIT(15));
|
|
}
|
|
|
|
static void
|
|
pci_conf_print_type1(
|
|
#ifdef _KERNEL
|
|
pci_chipset_tag_t pc, pcitag_t tag,
|
|
#endif
|
|
const pcireg_t *regs
|
|
#ifdef _KERNEL
|
|
, int sizebars
|
|
#endif
|
|
)
|
|
{
|
|
int off, width;
|
|
pcireg_t rval;
|
|
|
|
/*
|
|
* XXX these need to be printed in more detail, need to be
|
|
* XXX checked against specs/docs, etc.
|
|
*
|
|
* This layout was cribbed from the TI PCI2030 PCI-to-PCI
|
|
* Bridge chip documentation, and may not be correct with
|
|
* respect to various standards. (XXX)
|
|
*/
|
|
|
|
for (off = 0x10; off < 0x18; off += width) {
|
|
#ifdef _KERNEL
|
|
width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
|
|
#else
|
|
width = pci_conf_print_bar(regs, off, NULL);
|
|
#endif
|
|
}
|
|
|
|
printf(" Primary bus number: 0x%02x\n",
|
|
(regs[o2i(0x18)] >> 0) & 0xff);
|
|
printf(" Secondary bus number: 0x%02x\n",
|
|
(regs[o2i(0x18)] >> 8) & 0xff);
|
|
printf(" Subordinate bus number: 0x%02x\n",
|
|
(regs[o2i(0x18)] >> 16) & 0xff);
|
|
printf(" Secondary bus latency timer: 0x%02x\n",
|
|
(regs[o2i(0x18)] >> 24) & 0xff);
|
|
|
|
pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16)));
|
|
|
|
/* XXX Print more prettily */
|
|
printf(" I/O region:\n");
|
|
printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff);
|
|
printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff);
|
|
printf(" base upper 16 bits register: 0x%04x\n",
|
|
(regs[o2i(0x30)] >> 0) & 0xffff);
|
|
printf(" limit upper 16 bits register: 0x%04x\n",
|
|
(regs[o2i(0x30)] >> 16) & 0xffff);
|
|
|
|
/* XXX Print more prettily */
|
|
printf(" Memory region:\n");
|
|
printf(" base register: 0x%04x\n",
|
|
(regs[o2i(0x20)] >> 0) & 0xffff);
|
|
printf(" limit register: 0x%04x\n",
|
|
(regs[o2i(0x20)] >> 16) & 0xffff);
|
|
|
|
/* XXX Print more prettily */
|
|
printf(" Prefetchable memory region:\n");
|
|
printf(" base register: 0x%04x\n",
|
|
(regs[o2i(0x24)] >> 0) & 0xffff);
|
|
printf(" limit register: 0x%04x\n",
|
|
(regs[o2i(0x24)] >> 16) & 0xffff);
|
|
printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]);
|
|
printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]);
|
|
|
|
if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
|
|
printf(" Capability list pointer: 0x%02x\n",
|
|
PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
|
|
else
|
|
printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
|
|
|
|
/* XXX */
|
|
printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]);
|
|
|
|
printf(" Interrupt line: 0x%02x\n",
|
|
(regs[o2i(0x3c)] >> 0) & 0xff);
|
|
printf(" Interrupt pin: 0x%02x ",
|
|
(regs[o2i(0x3c)] >> 8) & 0xff);
|
|
switch ((regs[o2i(0x3c)] >> 8) & 0xff) {
|
|
case PCI_INTERRUPT_PIN_NONE:
|
|
printf("(none)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_A:
|
|
printf("(pin A)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_B:
|
|
printf("(pin B)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_C:
|
|
printf("(pin C)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_D:
|
|
printf("(pin D)");
|
|
break;
|
|
default:
|
|
printf("(? ? ?)");
|
|
break;
|
|
}
|
|
printf("\n");
|
|
rval = (regs[o2i(0x3c)] >> 16) & 0xffff;
|
|
printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */
|
|
onoff("Parity error response", 0x0001);
|
|
onoff("Secondary SERR forwarding", 0x0002);
|
|
onoff("ISA enable", 0x0004);
|
|
onoff("VGA enable", 0x0008);
|
|
onoff("Master abort reporting", 0x0020);
|
|
onoff("Secondary bus reset", 0x0040);
|
|
onoff("Fast back-to-back capable", 0x0080);
|
|
}
|
|
|
|
static void
|
|
pci_conf_print_type2(
|
|
#ifdef _KERNEL
|
|
pci_chipset_tag_t pc, pcitag_t tag,
|
|
#endif
|
|
const pcireg_t *regs
|
|
#ifdef _KERNEL
|
|
, int sizebars
|
|
#endif
|
|
)
|
|
{
|
|
pcireg_t rval;
|
|
|
|
/*
|
|
* XXX these need to be printed in more detail, need to be
|
|
* XXX checked against specs/docs, etc.
|
|
*
|
|
* This layout was cribbed from the TI PCI1420 PCI-to-CardBus
|
|
* controller chip documentation, and may not be correct with
|
|
* respect to various standards. (XXX)
|
|
*/
|
|
|
|
#ifdef _KERNEL
|
|
pci_conf_print_bar(pc, tag, regs, 0x10,
|
|
"CardBus socket/ExCA registers", sizebars);
|
|
#else
|
|
pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers");
|
|
#endif
|
|
|
|
if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
|
|
printf(" Capability list pointer: 0x%02x\n",
|
|
PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]));
|
|
else
|
|
printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n",
|
|
__SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0)));
|
|
pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16)));
|
|
|
|
printf(" PCI bus number: 0x%02x\n",
|
|
(regs[o2i(0x18)] >> 0) & 0xff);
|
|
printf(" CardBus bus number: 0x%02x\n",
|
|
(regs[o2i(0x18)] >> 8) & 0xff);
|
|
printf(" Subordinate bus number: 0x%02x\n",
|
|
(regs[o2i(0x18)] >> 16) & 0xff);
|
|
printf(" CardBus latency timer: 0x%02x\n",
|
|
(regs[o2i(0x18)] >> 24) & 0xff);
|
|
|
|
/* XXX Print more prettily */
|
|
printf(" CardBus memory region 0:\n");
|
|
printf(" base register: 0x%08x\n", regs[o2i(0x1c)]);
|
|
printf(" limit register: 0x%08x\n", regs[o2i(0x20)]);
|
|
printf(" CardBus memory region 1:\n");
|
|
printf(" base register: 0x%08x\n", regs[o2i(0x24)]);
|
|
printf(" limit register: 0x%08x\n", regs[o2i(0x28)]);
|
|
printf(" CardBus I/O region 0:\n");
|
|
printf(" base register: 0x%08x\n", regs[o2i(0x2c)]);
|
|
printf(" limit register: 0x%08x\n", regs[o2i(0x30)]);
|
|
printf(" CardBus I/O region 1:\n");
|
|
printf(" base register: 0x%08x\n", regs[o2i(0x34)]);
|
|
printf(" limit register: 0x%08x\n", regs[o2i(0x38)]);
|
|
|
|
printf(" Interrupt line: 0x%02x\n",
|
|
(regs[o2i(0x3c)] >> 0) & 0xff);
|
|
printf(" Interrupt pin: 0x%02x ",
|
|
(regs[o2i(0x3c)] >> 8) & 0xff);
|
|
switch ((regs[o2i(0x3c)] >> 8) & 0xff) {
|
|
case PCI_INTERRUPT_PIN_NONE:
|
|
printf("(none)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_A:
|
|
printf("(pin A)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_B:
|
|
printf("(pin B)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_C:
|
|
printf("(pin C)");
|
|
break;
|
|
case PCI_INTERRUPT_PIN_D:
|
|
printf("(pin D)");
|
|
break;
|
|
default:
|
|
printf("(? ? ?)");
|
|
break;
|
|
}
|
|
printf("\n");
|
|
rval = (regs[o2i(0x3c)] >> 16) & 0xffff;
|
|
printf(" Bridge control register: 0x%04x\n", rval);
|
|
onoff("Parity error response", __BIT(0));
|
|
onoff("SERR# enable", __BIT(1));
|
|
onoff("ISA enable", __BIT(2));
|
|
onoff("VGA enable", __BIT(3));
|
|
onoff("Master abort mode", __BIT(5));
|
|
onoff("Secondary (CardBus) bus reset", __BIT(6));
|
|
onoff("Functional interrupts routed by ExCA registers", __BIT(7));
|
|
onoff("Memory window 0 prefetchable", __BIT(8));
|
|
onoff("Memory window 1 prefetchable", __BIT(9));
|
|
onoff("Write posting enable", __BIT(10));
|
|
|
|
rval = regs[o2i(0x40)];
|
|
printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
|
|
printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
|
|
|
|
#ifdef _KERNEL
|
|
pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers",
|
|
sizebars);
|
|
#else
|
|
pci_conf_print_bar(regs, 0x44, "legacy-mode registers");
|
|
#endif
|
|
}
|
|
|
|
void
|
|
pci_conf_print(
|
|
#ifdef _KERNEL
|
|
pci_chipset_tag_t pc, pcitag_t tag,
|
|
void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)
|
|
#else
|
|
int pcifd, u_int bus, u_int dev, u_int func
|
|
#endif
|
|
)
|
|
{
|
|
pcireg_t regs[o2i(256)];
|
|
int off, capoff, endoff, hdrtype;
|
|
const char *typename;
|
|
#ifdef _KERNEL
|
|
void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int);
|
|
int sizebars;
|
|
#else
|
|
void (*typeprintfn)(const pcireg_t *);
|
|
#endif
|
|
|
|
printf("PCI configuration registers:\n");
|
|
|
|
for (off = 0; off < 256; off += 4) {
|
|
#ifdef _KERNEL
|
|
regs[o2i(off)] = pci_conf_read(pc, tag, off);
|
|
#else
|
|
if (pcibus_conf_read(pcifd, bus, dev, func, off,
|
|
®s[o2i(off)]) == -1)
|
|
regs[o2i(off)] = 0;
|
|
#endif
|
|
}
|
|
|
|
#ifdef _KERNEL
|
|
sizebars = 1;
|
|
if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE &&
|
|
PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST)
|
|
sizebars = 0;
|
|
#endif
|
|
|
|
/* common header */
|
|
printf(" Common header:\n");
|
|
pci_conf_print_regs(regs, 0, 16);
|
|
|
|
printf("\n");
|
|
#ifdef _KERNEL
|
|
pci_conf_print_common(pc, tag, regs);
|
|
#else
|
|
pci_conf_print_common(regs);
|
|
#endif
|
|
printf("\n");
|
|
|
|
/* type-dependent header */
|
|
hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]);
|
|
switch (hdrtype) { /* XXX make a table, eventually */
|
|
case 0:
|
|
/* Standard device header */
|
|
typename = "\"normal\" device";
|
|
typeprintfn = &pci_conf_print_type0;
|
|
capoff = PCI_CAPLISTPTR_REG;
|
|
endoff = 64;
|
|
break;
|
|
case 1:
|
|
/* PCI-PCI bridge header */
|
|
typename = "PCI-PCI bridge";
|
|
typeprintfn = &pci_conf_print_type1;
|
|
capoff = PCI_CAPLISTPTR_REG;
|
|
endoff = 64;
|
|
break;
|
|
case 2:
|
|
/* PCI-CardBus bridge header */
|
|
typename = "PCI-CardBus bridge";
|
|
typeprintfn = &pci_conf_print_type2;
|
|
capoff = PCI_CARDBUS_CAPLISTPTR_REG;
|
|
endoff = 72;
|
|
break;
|
|
default:
|
|
typename = NULL;
|
|
typeprintfn = 0;
|
|
capoff = -1;
|
|
endoff = 64;
|
|
break;
|
|
}
|
|
printf(" Type %d ", hdrtype);
|
|
if (typename != NULL)
|
|
printf("(%s) ", typename);
|
|
printf("header:\n");
|
|
pci_conf_print_regs(regs, 16, endoff);
|
|
printf("\n");
|
|
if (typeprintfn) {
|
|
#ifdef _KERNEL
|
|
(*typeprintfn)(pc, tag, regs, sizebars);
|
|
#else
|
|
(*typeprintfn)(regs);
|
|
#endif
|
|
} else
|
|
printf(" Don't know how to pretty-print type %d header.\n",
|
|
hdrtype);
|
|
printf("\n");
|
|
|
|
/* capability list, if present */
|
|
if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
|
|
&& (capoff > 0)) {
|
|
#ifdef _KERNEL
|
|
pci_conf_print_caplist(pc, tag, regs, capoff);
|
|
#else
|
|
pci_conf_print_caplist(regs, capoff);
|
|
#endif
|
|
printf("\n");
|
|
}
|
|
|
|
/* device-dependent header */
|
|
printf(" Device-dependent header:\n");
|
|
pci_conf_print_regs(regs, endoff, 256);
|
|
printf("\n");
|
|
#ifdef _KERNEL
|
|
if (printfn)
|
|
(*printfn)(pc, tag, regs);
|
|
else
|
|
printf(" Don't know how to pretty-print device-dependent header.\n");
|
|
printf("\n");
|
|
#endif /* _KERNEL */
|
|
}
|