409 lines
11 KiB
C
409 lines
11 KiB
C
/* $NetBSD: amdpm_smbus.c,v 1.16 2009/02/03 16:27:13 pgoyette Exp $ */
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/*
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* Copyright (c) 2005 Anil Gopinath (anil_public@yahoo.com)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* driver for SMBUS 1.0 host controller found in the
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* AMD-8111 HyperTransport I/O Hub
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: amdpm_smbus.c,v 1.16 2009/02/03 16:27:13 pgoyette Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/rnd.h>
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#include <sys/rwlock.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/i2c_bitbang.h>
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#include <dev/pci/amdpmreg.h>
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#include <dev/pci/amdpmvar.h>
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#include <dev/pci/amdpm_smbusreg.h>
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#ifdef __i386__
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#include "opt_xbox.h"
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#endif
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#ifdef XBOX
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extern int arch_i386_is_xbox;
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#endif
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static int amdpm_smbus_acquire_bus(void *, int);
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static void amdpm_smbus_release_bus(void *, int);
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static int amdpm_smbus_exec(void *, i2c_op_t, i2c_addr_t, const void *,
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size_t, void *, size_t, int);
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static int amdpm_smbus_check_done(struct amdpm_softc *, i2c_op_t);
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static void amdpm_smbus_clear_gsr(struct amdpm_softc *);
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static uint16_t amdpm_smbus_get_gsr(struct amdpm_softc *);
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static int amdpm_smbus_quick(struct amdpm_softc *, i2c_op_t);
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static int amdpm_smbus_send_1(struct amdpm_softc *, uint8_t, i2c_op_t);
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static int amdpm_smbus_write_1(struct amdpm_softc *, uint8_t,
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uint8_t, i2c_op_t);
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static int amdpm_smbus_receive_1(struct amdpm_softc *, i2c_op_t);
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static int amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t, i2c_op_t);
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#ifdef XBOX
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static int amdpm_smbus_intr(void *);
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#endif
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void
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amdpm_smbus_attach(struct amdpm_softc *sc)
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{
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struct i2cbus_attach_args iba;
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#ifdef XBOX
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pci_intr_handle_t ih;
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const char *intrstr;
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#endif
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/* register with iic */
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sc->sc_i2c.ic_cookie = sc;
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sc->sc_i2c.ic_acquire_bus = amdpm_smbus_acquire_bus;
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sc->sc_i2c.ic_release_bus = amdpm_smbus_release_bus;
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sc->sc_i2c.ic_send_start = NULL;
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sc->sc_i2c.ic_send_stop = NULL;
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sc->sc_i2c.ic_initiate_xfer = NULL;
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sc->sc_i2c.ic_read_byte = NULL;
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sc->sc_i2c.ic_write_byte = NULL;
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sc->sc_i2c.ic_exec = amdpm_smbus_exec;
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rw_init(&sc->sc_rwlock);
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#ifdef XBOX
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#define XBOX_SMBA 0x8000
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#define XBOX_SMSIZE 256
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#define XBOX_INTRLINE 12
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#define XBOX_REG_ACPI_PM1a_EN 0x02
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#define XBOX_REG_ACPI_PM1a_EN_TIMER 0x01
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/* XXX pci0 dev 1 function 2 "System Management" doesn't probe */
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if (arch_i386_is_xbox) {
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uint16_t val;
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sc->sc_pa->pa_intrline = XBOX_INTRLINE;
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if (bus_space_map(sc->sc_iot, XBOX_SMBA, XBOX_SMSIZE,
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0, &sc->sc_sm_ioh) == 0) {
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aprint_normal_dev(&sc->sc_dev, "system management at 0x%04x\n", XBOX_SMBA);
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/* Disable PM ACPI timer SCI interrupt */
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val = bus_space_read_2(sc->sc_iot, sc->sc_sm_ioh,
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XBOX_REG_ACPI_PM1a_EN);
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bus_space_write_2(sc->sc_iot, sc->sc_sm_ioh,
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XBOX_REG_ACPI_PM1a_EN,
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val & ~XBOX_REG_ACPI_PM1a_EN_TIMER);
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}
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}
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if (pci_intr_map(sc->sc_pa, &ih))
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aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n");
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else {
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intrstr = pci_intr_string(sc->sc_pc, ih);
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sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_BIO,
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amdpm_smbus_intr, sc);
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if (sc->sc_ih != NULL)
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aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n",
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intrstr);
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}
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#endif
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iba.iba_tag = &sc->sc_i2c;
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(void)config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print);
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}
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#ifdef XBOX
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static int
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amdpm_smbus_intr(void *cookie)
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{
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struct amdpm_softc *sc;
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uint32_t status;
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sc = (struct amdpm_softc *)cookie;
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if (arch_i386_is_xbox) {
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status = bus_space_read_4(sc->sc_iot, sc->sc_sm_ioh, 0x20);
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bus_space_write_4(sc->sc_iot, sc->sc_sm_ioh, 0x20, status);
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if (status & 2)
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return iic_smbus_intr(&sc->sc_i2c);
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}
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return 0;
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}
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#endif
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static int
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amdpm_smbus_acquire_bus(void *cookie, int flags)
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{
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struct amdpm_softc *sc = cookie;
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rw_enter(&sc->sc_rwlock, RW_WRITER);
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return 0;
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}
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static void
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amdpm_smbus_release_bus(void *cookie, int flags)
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{
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struct amdpm_softc *sc = cookie;
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rw_exit(&sc->sc_rwlock);
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}
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static int
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amdpm_smbus_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmd,
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size_t cmdlen, void *vbuf, size_t buflen, int flags)
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{
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struct amdpm_softc *sc = (struct amdpm_softc *) cookie;
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sc->sc_smbus_slaveaddr = addr;
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uint8_t *p = vbuf;
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int rv;
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if ((cmdlen == 0) && (buflen == 0))
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return amdpm_smbus_quick(sc, op);
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if (I2C_OP_READ_P(op) && (cmdlen == 0) && (buflen == 1)) {
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rv = amdpm_smbus_receive_1(sc, op);
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if (rv == -1)
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return -1;
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*p = (uint8_t)rv;
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return 0;
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}
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if ((I2C_OP_READ_P(op)) && (cmdlen == 1) && (buflen == 1)) {
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rv = amdpm_smbus_read_1(sc, *(const uint8_t *)cmd, op);
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if (rv == -1)
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return -1;
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*p = (uint8_t)rv;
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return 0;
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}
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if ((I2C_OP_WRITE_P(op)) && (cmdlen == 0) && (buflen == 1))
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return amdpm_smbus_send_1(sc, *(uint8_t*)vbuf, op);
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if ((I2C_OP_WRITE_P(op)) && (cmdlen == 1) && (buflen == 1))
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return amdpm_smbus_write_1(sc,
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*(const uint8_t*)cmd,
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*(uint8_t*)vbuf,
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op);
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return -1;
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}
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static int
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amdpm_smbus_check_done(struct amdpm_softc *sc, i2c_op_t op)
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{
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int i;
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for (i = 0; i < 1000; i++) {
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/* check gsr and wait till cycle is done */
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uint16_t data = amdpm_smbus_get_gsr(sc);
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if (data & AMDPM_8111_GSR_CYCLE_DONE)
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return 0;
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}
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if (!(op & I2C_F_POLL))
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delay(1);
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return -1;
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}
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static void
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amdpm_smbus_clear_gsr(struct amdpm_softc *sc)
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{
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/* clear register */
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uint16_t data = 0xFFFF;
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int off = (sc->sc_nforce ? 0xe0 : 0);
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_STAT - off, data);
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}
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static uint16_t
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amdpm_smbus_get_gsr(struct amdpm_softc *sc)
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{
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int off = (sc->sc_nforce ? 0xe0 : 0);
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return bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_STAT - off);
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}
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static int
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amdpm_smbus_quick(struct amdpm_softc *sc, i2c_op_t op)
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{
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uint16_t data = 0;
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int off = (sc->sc_nforce ? 0xe0 : 0);
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/* first clear gsr */
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amdpm_smbus_clear_gsr(sc);
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/* write smbus slave address and read/write bit to register */
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data = sc->sc_smbus_slaveaddr;
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data <<= 1;
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if (I2C_OP_READ_P(op))
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data |= AMDPM_8111_SMBUS_READ;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTADDR - off, data);
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/* host start */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_CTRL - off,
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AMDPM_8111_SMBUS_GSR_QUICK);
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return amdpm_smbus_check_done(sc, op);
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}
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static int
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amdpm_smbus_send_1(struct amdpm_softc *sc, uint8_t val, i2c_op_t op)
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{
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uint16_t data = 0;
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int off = (sc->sc_nforce ? 0xe0 : 0);
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/* first clear gsr */
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amdpm_smbus_clear_gsr(sc);
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/* write smbus slave address to register */
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data = sc->sc_smbus_slaveaddr;
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data <<= 1;
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data |= AMDPM_8111_SMBUS_SEND;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTADDR - off, data);
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data = val;
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/* store data */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTDATA - off, data);
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/* host start */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_CTRL - off,
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AMDPM_8111_SMBUS_GSR_SB);
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return amdpm_smbus_check_done(sc, op);
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}
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static int
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amdpm_smbus_write_1(struct amdpm_softc *sc, uint8_t cmd, uint8_t val,
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i2c_op_t op)
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{
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uint16_t data = 0;
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int off = (sc->sc_nforce ? 0xe0 : 0);
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/* first clear gsr */
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amdpm_smbus_clear_gsr(sc);
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data = sc->sc_smbus_slaveaddr;
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data <<= 1;
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data |= AMDPM_8111_SMBUS_WRITE;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTADDR - off, data);
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data = val;
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/* store cmd */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTCMD - off, cmd);
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/* store data */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTDATA - off, data);
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/* host start */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_WB);
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return amdpm_smbus_check_done(sc, op);
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}
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static int
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amdpm_smbus_receive_1(struct amdpm_softc *sc, i2c_op_t op)
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{
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uint16_t data = 0;
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int off = (sc->sc_nforce ? 0xe0 : 0);
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/* first clear gsr */
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amdpm_smbus_clear_gsr(sc);
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/* write smbus slave address to register */
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data = sc->sc_smbus_slaveaddr;
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data <<= 1;
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data |= AMDPM_8111_SMBUS_RX;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTADDR - off, data);
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/* start smbus cycle */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RXB);
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/* check for errors */
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if (amdpm_smbus_check_done(sc, op) < 0)
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return -1;
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/* read data */
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data = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTDATA - off);
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uint8_t ret = (uint8_t)(data & 0x00FF);
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return ret;
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}
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static int
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amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t cmd, i2c_op_t op)
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{
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uint16_t data = 0;
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uint8_t ret;
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int off = (sc->sc_nforce ? 0xe0 : 0);
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/* first clear gsr */
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amdpm_smbus_clear_gsr(sc);
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/* write smbus slave address to register */
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data = sc->sc_smbus_slaveaddr;
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data <<= 1;
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data |= AMDPM_8111_SMBUS_READ;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTADDR - off, data);
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/* store cmd */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTCMD - off, cmd);
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/* host start */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB);
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/* check for errors */
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if (amdpm_smbus_check_done(sc, op) < 0)
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return -1;
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/* store data */
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data = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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AMDPM_8111_SMBUS_HOSTDATA - off);
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ret = (uint8_t)(data & 0x00FF);
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return ret;
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}
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