443 lines
12 KiB
C
443 lines
12 KiB
C
/* $NetBSD: z8530sc.c,v 1.30 2009/05/22 03:51:30 mrg Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)zs.c 8.1 (Berkeley) 7/19/93
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*/
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/*
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* Copyright (c) 1994 Gordon W. Ross
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)zs.c 8.1 (Berkeley) 7/19/93
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*/
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/*
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* Zilog Z8530 Dual UART driver (common part)
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*
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* This file contains the machine-independent parts of the
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* driver common to tty and keyboard/mouse sub-drivers.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: z8530sc.c,v 1.30 2009/05/22 03:51:30 mrg Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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#include <dev/ic/z8530reg.h>
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#include <machine/z8530var.h>
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void
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zs_break(struct zs_chanstate *cs, int set)
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{
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if (set) {
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cs->cs_preg[5] |= ZSWR5_BREAK;
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cs->cs_creg[5] |= ZSWR5_BREAK;
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} else {
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cs->cs_preg[5] &= ~ZSWR5_BREAK;
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cs->cs_creg[5] &= ~ZSWR5_BREAK;
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}
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zs_write_reg(cs, 5, cs->cs_creg[5]);
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}
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/*
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* drain on-chip fifo
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*/
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void
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zs_iflush(struct zs_chanstate *cs)
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{
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uint8_t c, rr0, rr1;
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int i;
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/*
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* Count how many times we loop. Some systems, such as some
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* Apple PowerBooks, claim to have SCC's which they really don't.
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*/
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for (i = 0; i < 32; i++) {
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/* Is there input available? */
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rr0 = zs_read_csr(cs);
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if ((rr0 & ZSRR0_RX_READY) == 0)
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break;
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/*
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* First read the status, because reading the data
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* destroys the status of this char.
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*/
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rr1 = zs_read_reg(cs, 1);
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c = zs_read_data(cs);
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if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
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/* Clear the receive error. */
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zs_write_csr(cs, ZSWR0_RESET_ERRORS);
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}
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}
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}
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/*
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* Write the given register set to the given zs channel in the proper order.
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* The channel must not be transmitting at the time. The receiver will
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* be disabled for the time it takes to write all the registers.
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* Call this with interrupts disabled.
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*/
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void
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zs_loadchannelregs(struct zs_chanstate *cs)
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{
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uint8_t *reg, v;
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zs_write_csr(cs, ZSM_RESET_ERR); /* XXX: reset error condition */
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#if 1
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/*
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* XXX: Is this really a good idea?
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* XXX: Should go elsewhere! -gwr
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*/
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zs_iflush(cs); /* XXX */
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#endif
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if (cs->cs_ctl_chan != NULL)
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v = ((cs->cs_ctl_chan->cs_creg[5] & (ZSWR5_RTS | ZSWR5_DTR)) !=
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(cs->cs_ctl_chan->cs_preg[5] & (ZSWR5_RTS | ZSWR5_DTR)));
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else
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v = 0;
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if (memcmp((void *)cs->cs_preg, (void *)cs->cs_creg, 16) == 0 && !v)
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return; /* only change if values are different */
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/* Copy "pending" regs to "current" */
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memcpy((void *)cs->cs_creg, (void *)cs->cs_preg, 16);
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reg = cs->cs_creg; /* current regs */
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/* disable interrupts */
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zs_write_reg(cs, 1, reg[1] & ~ZSWR1_IMASK);
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/* baud clock divisor, stop bits, parity */
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zs_write_reg(cs, 4, reg[4]);
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/* misc. TX/RX control bits */
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zs_write_reg(cs, 10, reg[10]);
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/* char size, enable (RX/TX) */
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zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
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zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
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/* synchronous mode stuff */
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zs_write_reg(cs, 6, reg[6]);
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zs_write_reg(cs, 7, reg[7]);
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#if 0
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/*
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* Registers 2 and 9 are special because they are
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* actually common to both channels, but must be
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* programmed through channel A. The "zsc" attach
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* function takes care of setting these registers
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* and they should not be touched thereafter.
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*/
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/* interrupt vector */
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zs_write_reg(cs, 2, reg[2]);
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/* master interrupt control */
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zs_write_reg(cs, 9, reg[9]);
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#endif
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/* Shut down the BRG */
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zs_write_reg(cs, 14, reg[14] & ~ZSWR14_BAUD_ENA);
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#ifdef ZS_MD_SETCLK
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/* Let the MD code setup any external clock. */
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ZS_MD_SETCLK(cs);
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#endif /* ZS_MD_SETCLK */
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/* clock mode control */
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zs_write_reg(cs, 11, reg[11]);
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/* baud rate (lo/hi) */
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zs_write_reg(cs, 12, reg[12]);
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zs_write_reg(cs, 13, reg[13]);
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/* Misc. control bits */
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zs_write_reg(cs, 14, reg[14]);
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/* which lines cause status interrupts */
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zs_write_reg(cs, 15, reg[15]);
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/*
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* Zilog docs recommend resetting external status twice at this
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* point. Mainly as the status bits are latched, and the first
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* interrupt clear might unlatch them to new values, generating
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* a second interrupt request.
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*/
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zs_write_csr(cs, ZSM_RESET_STINT);
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zs_write_csr(cs, ZSM_RESET_STINT);
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/* char size, enable (RX/TX)*/
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zs_write_reg(cs, 3, reg[3]);
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zs_write_reg(cs, 5, reg[5]);
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/* Write the status bits on the alternate channel also. */
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if (cs->cs_ctl_chan != NULL) {
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v = cs->cs_ctl_chan->cs_preg[5];
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cs->cs_ctl_chan->cs_creg[5] = v;
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zs_write_reg(cs->cs_ctl_chan, 5, v);
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}
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/* interrupt enables: RX, TX, STATUS */
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zs_write_reg(cs, 1, reg[1]);
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}
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void
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zs_lock_init(struct zs_chanstate *cs)
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{
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mutex_init(&cs->cs_lock, MUTEX_NODEBUG, IPL_ZS);
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}
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void
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zs_lock_chan(struct zs_chanstate *cs)
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{
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mutex_spin_enter(&cs->cs_lock);
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}
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void
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zs_unlock_chan(struct zs_chanstate *cs)
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{
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mutex_spin_exit(&cs->cs_lock);
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}
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/*
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* ZS hardware interrupt. Scan all ZS channels. NB: we know here that
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* channels are kept in (A,B) pairs.
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*
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* Do just a little, then get out; set a software interrupt if more
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* work is needed.
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*
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* We deliberately ignore the vectoring Zilog gives us, and match up
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* only the number of `reset interrupt under service' operations, not
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* the order.
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*/
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int
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zsc_intr_hard(void *arg)
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{
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struct zsc_softc *zsc = arg;
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struct zs_chanstate *cs0, *cs1;
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int handled;
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uint8_t rr3;
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handled = 0;
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/* First look at channel A. */
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cs0 = zsc->zsc_cs[0];
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cs1 = zsc->zsc_cs[1];
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/*
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* We have to clear interrupt first to avoid a race condition,
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* but it will be done in each MD handler.
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*/
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for (;;) {
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/* Lock both channels */
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mutex_spin_enter(&cs1->cs_lock);
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mutex_spin_enter(&cs0->cs_lock);
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/* Note: only channel A has an RR3 */
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rr3 = zs_read_reg(cs0, 3);
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if ((rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT |
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ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) == 0) {
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mutex_spin_exit(&cs0->cs_lock);
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mutex_spin_exit(&cs1->cs_lock);
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break;
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}
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handled = 1;
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/* First look at channel A. */
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if (rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT))
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zs_write_csr(cs0, ZSWR0_CLR_INTR);
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if (rr3 & ZSRR3_IP_A_RX)
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(*cs0->cs_ops->zsop_rxint)(cs0);
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if (rr3 & ZSRR3_IP_A_STAT)
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(*cs0->cs_ops->zsop_stint)(cs0, 0);
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if (rr3 & ZSRR3_IP_A_TX)
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(*cs0->cs_ops->zsop_txint)(cs0);
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/* Done with channel A */
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mutex_spin_exit(&cs0->cs_lock);
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/* Now look at channel B. */
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if (rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT))
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zs_write_csr(cs1, ZSWR0_CLR_INTR);
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if (rr3 & ZSRR3_IP_B_RX)
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(*cs1->cs_ops->zsop_rxint)(cs1);
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if (rr3 & ZSRR3_IP_B_STAT)
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(*cs1->cs_ops->zsop_stint)(cs1, 0);
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if (rr3 & ZSRR3_IP_B_TX)
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(*cs1->cs_ops->zsop_txint)(cs1);
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mutex_spin_exit(&cs1->cs_lock);
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}
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/* Note: caller will check cs_x->cs_softreq and DTRT. */
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return handled;
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}
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/*
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* ZS software interrupt. Scan all channels for deferred interrupts.
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*/
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int
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zsc_intr_soft(void *arg)
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{
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struct zsc_softc *zsc = arg;
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struct zs_chanstate *cs;
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int rval, chan;
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rval = 0;
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for (chan = 0; chan < 2; chan++) {
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cs = zsc->zsc_cs[chan];
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/*
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* The softint flag can be safely cleared once
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* we have decided to call the softint routine.
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* (No need to do splzs() first.)
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*/
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if (cs->cs_softreq) {
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cs->cs_softreq = 0;
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(*cs->cs_ops->zsop_softint)(cs);
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rval++;
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}
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}
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return (rval);
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}
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/*
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* Provide a null zs "ops" vector.
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*/
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static void zsnull_rxint (struct zs_chanstate *);
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static void zsnull_stint (struct zs_chanstate *, int);
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static void zsnull_txint (struct zs_chanstate *);
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static void zsnull_softint(struct zs_chanstate *);
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static void
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zsnull_rxint(struct zs_chanstate *cs)
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{
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/* Ask for softint() call. */
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cs->cs_softreq = 1;
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}
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static void
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zsnull_stint(struct zs_chanstate *cs, int force)
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{
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/* Ask for softint() call. */
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cs->cs_softreq = 1;
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}
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static void
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zsnull_txint(struct zs_chanstate *cs)
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{
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/* Ask for softint() call. */
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cs->cs_softreq = 1;
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}
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static void
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zsnull_softint(struct zs_chanstate *cs)
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{
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zs_write_reg(cs, 1, 0);
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zs_write_reg(cs, 15, 0);
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}
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struct zsops zsops_null = {
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zsnull_rxint, /* receive char available */
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zsnull_stint, /* external/status */
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zsnull_txint, /* xmit buffer empty */
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zsnull_softint, /* process software interrupt */
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};
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