190 lines
6.6 KiB
C
190 lines
6.6 KiB
C
/* $NetBSD: wdcvar.h,v 1.91 2010/11/05 18:07:24 jakllsch Exp $ */
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/*-
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* Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_WDCVAR_H_
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#define _DEV_IC_WDCVAR_H_
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#include <sys/callout.h>
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#include <dev/ata/ataconf.h>
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#include <dev/ic/wdcreg.h>
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#define WAITTIME (10 * hz) /* time to wait for a completion */
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/* this is a lot for hard drives, but not for cdroms */
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#define WDC_NREG 8 /* number of command registers */
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#define WDC_NSHADOWREG 2 /* number of command "shadow" registers */
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struct wdc_regs {
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/* Our registers */
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bus_space_tag_t cmd_iot;
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bus_space_handle_t cmd_baseioh;
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bus_size_t cmd_ios;
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bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG];
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bus_space_tag_t ctl_iot;
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bus_space_handle_t ctl_ioh;
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bus_size_t ctl_ios;
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/* data32{iot,ioh} are only used for 32-bit data xfers */
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bus_space_tag_t data32iot;
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bus_space_handle_t data32ioh;
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/* SATA native registers */
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bus_space_tag_t sata_iot;
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bus_space_handle_t sata_baseioh;
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bus_space_handle_t sata_control;
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bus_space_handle_t sata_status;
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bus_space_handle_t sata_error;
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};
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/*
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* Per-controller data
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*/
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struct wdc_softc {
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struct atac_softc sc_atac; /* generic ATA controller info */
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struct wdc_regs *regs; /* register array (per-channel) */
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int cap; /* controller capabilities */
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#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
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#define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
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#define WDC_CAPABILITY_WIDEREGS 0x0400 /* Ctrl has wide (16bit) registers */
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#if NATA_DMA || NATA_PIOBM
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/* if WDC_CAPABILITY_DMA set in 'cap' */
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void *dma_arg;
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int (*dma_init)(void *, int, int, void *, size_t, int);
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void (*dma_start)(void *, int, int);
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int (*dma_finish)(void *, int, int, int);
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#if NATA_PIOBM
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void (*piobm_start)(void *, int, int, int, int, int);
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void (*piobm_done)(void *, int, int);
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#endif
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/* flags passed to dma_init */
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#define WDC_DMA_READ 0x01
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#define WDC_DMA_IRQW 0x02
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#define WDC_DMA_LBA48 0x04
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#define WDC_DMA_PIOBM_ATA 0x08
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#define WDC_DMA_PIOBM_ATAPI 0x10
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#if NATA_PIOBM
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/* flags passed to piobm_start */
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#define WDC_PIOBM_XFER_IRQ 0x01
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#endif
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/* values passed to dma_finish */
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#define WDC_DMAEND_END 0 /* check for proper end of a DMA xfer */
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#define WDC_DMAEND_ABRT 1 /* abort a DMA xfer, verbose */
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#define WDC_DMAEND_ABRT_QUIET 2 /* abort a DMA xfer, quiet */
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int dma_status; /* status returned from dma_finish() */
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#define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */
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#define WDC_DMAST_ERR 0x02 /* DMA error */
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#define WDC_DMAST_UNDER 0x04 /* DMA underrun */
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#endif /* NATA_DMA || NATA_PIOBM */
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/* Optional callback to select drive. */
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void (*select)(struct ata_channel *,int);
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/* Optional callback to ack IRQ. */
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void (*irqack)(struct ata_channel *);
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/* Optional callback to perform a bus reset */
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void (*reset)(struct ata_channel *, int);
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/* overridden if the backend has a different data transfer method */
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void (*datain_pio)(struct ata_channel *, int, void *, size_t);
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void (*dataout_pio)(struct ata_channel *, int, void *, size_t);
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};
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/* Given an ata_channel, get the wdc_softc. */
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#define CHAN_TO_WDC(chp) ((struct wdc_softc *)(chp)->ch_atac)
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/* Given an ata_channel, get the wdc_regs. */
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#define CHAN_TO_WDC_REGS(chp) (&CHAN_TO_WDC(chp)->regs[(chp)->ch_channel])
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/*
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* Public functions which can be called by ATA or ATAPI specific parts,
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* or bus-specific backends.
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*/
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void wdc_allocate_regs(struct wdc_softc *);
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void wdc_init_shadow_regs(struct ata_channel *);
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int wdcprobe(struct ata_channel *);
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void wdcattach(struct ata_channel *);
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int wdcdetach(device_t, int);
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void wdc_childdetached(device_t, device_t);
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int wdcintr(void *);
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void wdc_sataprobe(struct ata_channel *);
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void wdc_drvprobe(struct ata_channel *);
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void wdcrestart(void*);
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int wdcwait(struct ata_channel *, int, int, int, int);
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#define WDCWAIT_OK 0 /* we have what we asked */
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#define WDCWAIT_TOUT -1 /* timed out */
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#define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */
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void wdcbit_bucket(struct ata_channel *, int);
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int wdc_dmawait(struct ata_channel *, struct ata_xfer *, int);
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void wdccommand(struct ata_channel *, u_int8_t, u_int8_t, u_int16_t,
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u_int8_t, u_int8_t, u_int8_t, u_int8_t);
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void wdccommandext(struct ata_channel *, u_int8_t, u_int8_t, u_int64_t,
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u_int16_t);
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void wdccommandshort(struct ata_channel *, int, int);
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void wdctimeout(void *arg);
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void wdc_reset_drive(struct ata_drive_datas *, int);
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void wdc_reset_channel(struct ata_channel *, int);
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void wdc_do_reset(struct ata_channel *, int);
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int wdc_exec_command(struct ata_drive_datas *, struct ata_command*);
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/*
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* ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
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* command is aborted.
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*/
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#define wdc_wait_for_drq(chp, timeout, flags) \
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wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags))
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#define wdc_wait_for_unbusy(chp, timeout, flags) \
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wdcwait((chp), 0, 0, (timeout), (flags))
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#define wdc_wait_for_ready(chp, timeout, flags) \
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wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags))
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/* ATA/ATAPI specs says a device can take 31s to reset */
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#define WDC_RESET_WAIT 31000
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void wdc_atapibus_attach(struct atabus_softc *);
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#endif /* _DEV_IC_WDCVAR_H_ */
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