454 lines
14 KiB
C
454 lines
14 KiB
C
/* $NetBSD: atwvar.h,v 1.37 2010/03/14 21:25:59 dyoung Exp $ */
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/*
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* Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_ATWVAR_H_
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#define _DEV_IC_ATWVAR_H_
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#include <sys/queue.h>
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#include <sys/callout.h>
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#include <sys/time.h>
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/*
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* Transmit descriptor list size. This is arbitrary, but allocate
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* enough descriptors for 64 pending transmissions and 16 segments
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* per packet. Since a descriptor holds 2 buffer addresses, that's
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* 8 descriptors per packet. This MUST work out to a power of 2.
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*/
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#define ATW_NTXSEGS 16
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#define ATW_TXQUEUELEN 64
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#define ATW_NTXDESC (ATW_TXQUEUELEN * ATW_NTXSEGS)
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#define ATW_NTXDESC_MASK (ATW_NTXDESC - 1)
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#define ATW_NEXTTX(x) ((x + 1) & ATW_NTXDESC_MASK)
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/*
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* Receive descriptor list size. We have one Rx buffer per incoming
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* packet, so this logic is a little simpler.
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*/
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#define ATW_NRXDESC 64
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#define ATW_NRXDESC_MASK (ATW_NRXDESC - 1)
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#define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK)
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/*
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* Control structures are DMA'd to the ADM8211 chip. We allocate them in
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* a single clump that maps to a single DMA segment to make several things
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* easier.
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*/
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struct atw_control_data {
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/*
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* The transmit descriptors.
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*/
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struct atw_txdesc acd_txdescs[ATW_NTXDESC];
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/*
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* The receive descriptors.
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*/
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struct atw_rxdesc acd_rxdescs[ATW_NRXDESC];
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};
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#define ATW_CDOFF(x) offsetof(struct atw_control_data, x)
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#define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)])
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#define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)])
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/*
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* Software state for transmit jobs.
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*/
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struct atw_txsoft {
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struct mbuf *txs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t txs_dmamap; /* our DMA map */
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int txs_firstdesc; /* first descriptor in packet */
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int txs_lastdesc; /* last descriptor in packet */
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int txs_ndescs; /* number of descriptors */
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struct ieee80211_duration txs_d0;
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struct ieee80211_duration txs_dn;
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SIMPLEQ_ENTRY(atw_txsoft) txs_q;
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};
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SIMPLEQ_HEAD(atw_txsq, atw_txsoft);
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/*
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* Software state for receive jobs.
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*/
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struct atw_rxsoft {
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struct mbuf *rxs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t rxs_dmamap; /* our DMA map */
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};
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/*
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* Table which describes the transmit threshold mode. We generally
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* start at index 0. Whenever we get a transmit underrun, we increment
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* our index, falling back if we encounter the NULL terminator.
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*/
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struct atw_txthresh_tab {
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u_int32_t txth_opmode; /* OPMODE bits */
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const char *txth_name; /* name of mode */
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};
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#define ATW_TXTHRESH_TAB_LO_RATE { \
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{ ATW_NAR_TR_L64, "64 bytes" }, \
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{ ATW_NAR_TR_L160, "160 bytes" }, \
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{ ATW_NAR_TR_L192, "192 bytes" }, \
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{ ATW_NAR_SF, "store and forward" }, \
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{ 0, NULL }, \
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}
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#define ATW_TXTHRESH_TAB_HI_RATE { \
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{ ATW_NAR_TR_H96, "96 bytes" }, \
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{ ATW_NAR_TR_H288, "288 bytes" }, \
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{ ATW_NAR_TR_H544, "544 bytes" }, \
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{ ATW_NAR_SF, "store and forward" }, \
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{ 0, NULL }, \
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}
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enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD = 1,
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ATW_RFTYPE_MARVEL = 2 };
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enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD = 1,
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ATW_BBPTYPE_MARVEL = 2, ATW_C_BBPTYPE_RFMD = 5 };
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/* Radio capture format for ADMtek. */
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#define ATW_RX_RADIOTAP_PRESENT \
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((1 << IEEE80211_RADIOTAP_FLAGS) | (1 << IEEE80211_RADIOTAP_RATE) | \
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(1 << IEEE80211_RADIOTAP_CHANNEL) | \
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(1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL))
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struct atw_rx_radiotap_header {
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struct ieee80211_radiotap_header ar_ihdr;
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uint8_t ar_flags;
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uint8_t ar_rate;
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uint16_t ar_chan_freq;
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uint16_t ar_chan_flags;
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uint8_t ar_antsignal;
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} __packed;
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#define ATW_TX_RADIOTAP_PRESENT ((1 << IEEE80211_RADIOTAP_RATE) | \
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(1 << IEEE80211_RADIOTAP_CHANNEL))
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struct atw_tx_radiotap_header {
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struct ieee80211_radiotap_header at_ihdr;
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uint8_t at_rate;
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uint8_t at_pad;
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uint16_t at_chan_freq;
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uint16_t at_chan_flags;
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} __packed;
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enum atw_revision {
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ATW_REVISION_AB = 0x11, /* ADM8211A */
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ATW_REVISION_AF = 0x15, /* ADM8211A? */
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ATW_REVISION_BA = 0x20, /* ADM8211B */
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ATW_REVISION_CA = 0x30 /* ADM8211C/CR */
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};
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struct atw_softc {
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device_t sc_dev;
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device_suspensor_t sc_suspensor;
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pmf_qual_t sc_qual;
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struct ethercom sc_ec;
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struct ieee80211com sc_ic;
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int (*sc_newstate)(struct ieee80211com *,
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enum ieee80211_state, int);
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void (*sc_recv_mgmt)(struct ieee80211com *,
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struct mbuf *, struct ieee80211_node *,
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int, int, u_int32_t);
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struct ieee80211_node *(*sc_node_alloc)(struct ieee80211_node_table*);
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void (*sc_node_free)(struct ieee80211_node *);
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int sc_tx_timer;
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int sc_rescan_timer;
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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bus_dma_tag_t sc_dmat; /* bus dma tag */
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u_int32_t sc_cacheline; /* cache line size */
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u_int32_t sc_maxburst; /* maximum burst length */
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const struct atw_txthresh_tab *sc_txth;
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int sc_txthresh; /* current tx threshold */
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u_int sc_cur_chan; /* current channel */
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int sc_flags;
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u_int16_t *sc_srom;
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u_int16_t sc_sromsz;
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struct bpf_if * sc_radiobpf;
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bus_dma_segment_t sc_cdseg; /* control data memory */
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int sc_cdnseg; /* number of segments */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
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/*
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* Software state for transmit and receive descriptors.
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*/
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struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN];
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struct atw_rxsoft sc_rxsoft[ATW_NRXDESC];
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/*
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* Control data structures.
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*/
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struct atw_control_data *sc_control_data;
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#define sc_txdescs sc_control_data->acd_txdescs
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#define sc_rxdescs sc_control_data->acd_rxdescs
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#define sc_setup_desc sc_control_data->acd_setup_desc
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int sc_txfree; /* number of free Tx descriptors */
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int sc_txnext; /* next ready Tx descriptor */
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int sc_ntxsegs; /* number of transmit segs per pkt */
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struct atw_txsq sc_txfreeq; /* free Tx descsofts */
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struct atw_txsq sc_txdirtyq; /* dirty Tx descsofts */
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int sc_rxptr; /* next ready RX descriptor/descsoft */
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u_int32_t sc_busmode; /* copy of ATW_PAR */
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u_int32_t sc_opmode; /* copy of ATW_NAR */
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u_int32_t sc_inten; /* copy of ATW_IER */
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u_int32_t sc_wepctl; /* copy of ATW_WEPCTL */
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u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */
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u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */
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u_int32_t sc_linkint_mask;/* link-state interrupts mask */
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enum atw_rftype sc_rftype;
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enum atw_bbptype sc_bbptype;
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u_int32_t sc_synctl_rd;
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u_int32_t sc_synctl_wr;
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u_int32_t sc_bbpctl_rd;
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u_int32_t sc_bbpctl_wr;
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void (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *,
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int, u_int32_t);
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void (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *,
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int, u_int32_t);
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/* ADM8211 state variables. */
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u_int8_t sc_sram[ATW_SRAM_MAXSIZE];
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u_int sc_sramlen;
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u_int8_t sc_bssid[IEEE80211_ADDR_LEN];
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uint8_t sc_rev;
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uint8_t sc_rf3000_options1;
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uint8_t sc_rf3000_options2;
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struct evcnt sc_misc_ev;
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struct evcnt sc_workaround1_ev;
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struct evcnt sc_rxamatch_ev;
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struct evcnt sc_rxpkt1in_ev;
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struct evcnt sc_xmit_ev;
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struct evcnt sc_tuf_ev; /* transmit underflow errors */
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struct evcnt sc_tro_ev; /* transmit overrun */
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struct evcnt sc_trt_ev; /* retry count exceeded */
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struct evcnt sc_tlt_ev; /* lifetime exceeded */
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struct evcnt sc_sofbr_ev; /* packet size mismatch */
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struct evcnt sc_recv_ev;
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struct evcnt sc_crc16e_ev;
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struct evcnt sc_crc32e_ev;
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struct evcnt sc_icve_ev;
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struct evcnt sc_sfde_ev;
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struct evcnt sc_sige_ev;
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struct callout sc_scan_ch;
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union {
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struct atw_rx_radiotap_header tap;
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u_int8_t pad[64];
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} sc_rxtapu;
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union {
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struct atw_tx_radiotap_header tap;
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u_int8_t pad[64];
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} sc_txtapu;
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};
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#define sc_if sc_ec.ec_if
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#define sc_rxtap sc_rxtapu.tap
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#define sc_txtap sc_txtapu.tap
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/* XXX this is fragile. try not to introduce any u_int32_t's. */
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struct atw_frame {
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/*00*/ u_int8_t atw_dst[IEEE80211_ADDR_LEN];
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/*06*/ u_int8_t atw_rate; /* TX rate in 100Kbps */
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/*07*/ u_int8_t atw_service; /* 0 */
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/*08*/ u_int16_t atw_paylen; /* payload length */
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/*0a*/ u_int8_t atw_fc[2]; /* 802.11 Frame
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* Control
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*/
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/* 802.11 PLCP Length for first & last fragment */
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/*0c*/ u_int16_t atw_tail_plcplen;
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/*0e*/ u_int16_t atw_head_plcplen;
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/* 802.11 Duration for first & last fragment */
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/*10*/ u_int16_t atw_tail_dur;
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/*12*/ u_int16_t atw_head_dur;
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/*14*/ u_int8_t atw_addr4[IEEE80211_ADDR_LEN];
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union {
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struct {
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/*1a*/ u_int16_t hdrctl; /*transmission control*/
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/*1c*/ u_int16_t fragthr;/* fragmentation threshold
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* [0:11], zero [12:15].
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*/
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/*1e*/ u_int8_t fragnum;/* fragment number [4:7],
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* zero [0:3].
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*/
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/*1f*/ u_int8_t rtylmt; /* retry limit */
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/*20*/ u_int8_t wepkey0[4];/* ??? */
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/*24*/ u_int8_t wepkey1[4];/* ??? */
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/*28*/ u_int8_t wepkey2[4];/* ??? */
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/*2c*/ u_int8_t wepkey3[4];/* ??? */
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/*30*/ u_int8_t keyid;
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/*31*/ u_int8_t reserved0[7];
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} s1;
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struct {
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u_int8_t pad[6];
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struct ieee80211_frame ihdr;
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} s2;
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} u;
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} __packed;
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#define atw_hdrctl u.s1.hdrctl
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#define atw_fragthr u.s1.fragthr
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#define atw_fragnum u.s1.fragnum
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#define atw_rtylmt u.s1.rtylmt
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#define atw_keyid u.s1.keyid
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#define atw_ihdr u.s2.ihdr
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#define ATW_HDRCTL_SHORT_PREAMBLE __BIT(0) /* use short preamble */
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#define ATW_HDRCTL_MORE_FRAG __BIT(1) /* ??? from Linux */
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#define ATW_HDRCTL_MORE_DATA __BIT(2) /* ??? from Linux */
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#define ATW_HDRCTL_FRAG_NUM __BIT(3) /* ??? from Linux */
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#define ATW_HDRCTL_RTSCTS __BIT(4) /* send RTS */
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#define ATW_HDRCTL_WEP __BIT(5)
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/* MAC adds FCS? Linux calls this "enable extended header" */
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#define ATW_HDRCTL_UNKNOWN1 __BIT(15)
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#define ATW_HDRCTL_UNKNOWN2 __BIT(8)
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#define ATW_FRAGTHR_FRAGTHR_MASK __BITS(0, 11)
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#define ATW_FRAGNUM_FRAGNUM_MASK __BITS(4, 7)
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/* Values for sc_flags. */
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#define ATWF_MRL 0x00000001 /* memory read line okay */
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#define ATWF_MRM 0x00000002 /* memory read multi okay */
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#define ATWF_MWI 0x00000004 /* memory write inval okay */
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#define ATWF_SHORT_PREAMBLE 0x00000008 /* short preamble enabled */
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#define ATWF_ATTACHED 0x00000010 /* attach has succeeded */
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#define ATWF_ENABLED 0x00000020 /* chip is enabled */
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#define ATWF_WEP_SRAM_VALID 0x00000040 /* SRAM matches s/w state */
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#define ATW_CDTXADDR(sc, x) ((sc)->sc_cddma + ATW_CDTXOFF((x)))
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#define ATW_CDRXADDR(sc, x) ((sc)->sc_cddma + ATW_CDRXOFF((x)))
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#define ATW_CDTXSYNC(sc, x, n, ops) \
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do { \
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int __x, __n; \
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\
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__x = (x); \
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__n = (n); \
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\
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/* If it will wrap around, sync to the end of the ring. */ \
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if ((__x + __n) > ATW_NTXDESC) { \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * \
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(ATW_NTXDESC - __x), (ops)); \
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__n -= (ATW_NTXDESC - __x); \
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__x = 0; \
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} \
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\
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/* Now sync whatever is left. */ \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \
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} while (0)
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#define ATW_CDRXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops))
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/*
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* Note we rely on MCLBYTES being a power of two. Because the `length'
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* field is only 11 bits, we must subtract 1 from the length to avoid
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* having it truncated to 0!
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*/
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static inline void
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atw_init_rxdesc(struct atw_softc *sc, int x)
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{
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struct atw_rxsoft *rxs = &sc->sc_rxsoft[x];
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struct atw_rxdesc *rxd = &sc->sc_rxdescs[x];
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struct mbuf *m = rxs->rxs_mbuf;
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rxd->ar_buf1 =
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htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr);
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rxd->ar_buf2 = /* for descriptor chaining */
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htole32(ATW_CDRXADDR((sc), ATW_NEXTRX(x)));
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rxd->ar_ctlrssi =
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htole32(__SHIFTIN(((m->m_ext.ext_size - 1) & ~0x3U),
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ATW_RXCTL_RBS1_MASK) |
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0 /* ATW_RXCTL_RCH */ |
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(x == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0));
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rxd->ar_stat = htole32(ATW_RXSTAT_OWN);
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ATW_CDRXSYNC((sc), x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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}
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/* country codes from ADM8211 SROM */
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#define ATW_COUNTRY_FCC 0 /* USA 1-11 */
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#define ATW_COUNTRY_IC 1 /* Canada 1-11 */
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#define ATW_COUNTRY_ETSI 2 /* European Union (?) 1-13 */
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#define ATW_COUNTRY_SPAIN 3 /* 10-11 */
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#define ATW_COUNTRY_FRANCE 4 /* 10-13 */
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#define ATW_COUNTRY_MKK 5 /* Japan: 14 */
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#define ATW_COUNTRY_MKK2 6 /* Japan: 1-14 */
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/*
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* register space access macros
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*/
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#define ATW_READ(sc, reg) \
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bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
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#define ATW_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define ATW_SET(sc, reg, mask) \
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ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))
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#define ATW_CLR(sc, reg, mask) \
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ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))
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#define ATW_ISSET(sc, reg, mask) \
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(ATW_READ((sc), (reg)) & (mask))
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void atw_attach(struct atw_softc *);
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int atw_detach(struct atw_softc *);
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int atw_activate(device_t, enum devact);
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int atw_intr(void *arg);
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bool atw_shutdown(device_t, int);
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bool atw_suspend(device_t, const pmf_qual_t *);
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#endif /* _DEV_IC_ATWVAR_H_ */
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