1302 lines
31 KiB
C
1302 lines
31 KiB
C
/* $NetBSD: scsi.c,v 1.8 1996/02/14 02:44:59 thorpej Exp $ */
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/*
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* Copyright (c) 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Van Jacobson of Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)scsi.c 8.2 (Berkeley) 1/12/94
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*/
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#ifndef DEBUG
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#define DEBUG
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#endif
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/*
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* HP9000/3xx 98658 SCSI host adaptor driver.
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*/
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#include "scsi.h"
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#if NSCSI > 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/buf.h>
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#include <machine/cpu.h>
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#include <hp300/dev/device.h>
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#include <hp300/dev/scsivar.h>
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#include <hp300/dev/scsireg.h>
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#include <hp300/dev/dmavar.h>
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#include <hp300/hp300/isr.h>
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/*
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* SCSI delays
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* In u-seconds, primarily for state changes on the SPC.
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*/
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#define SCSI_CMD_WAIT 1000 /* wait per step of 'immediate' cmds */
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#define SCSI_DATA_WAIT 1000 /* wait per data in/out step */
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#define SCSI_INIT_WAIT 50000 /* wait per step (both) during init */
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extern void isrlink();
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extern void _insque();
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extern void _remque();
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int scsimatch(), scsigo(), scsixfer();
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void scsiattach(), scsistart(), scsidone(), scsifree(), scsireset();
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int scsiintr __P((void *));
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struct driver scsidriver = {
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scsimatch, scsiattach, "scsi", (int (*)())scsistart, scsigo, scsiintr,
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(int (*)())scsidone,
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};
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struct scsi_softc scsi_softc[NSCSI];
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int scsi_cmd_wait = SCSI_CMD_WAIT;
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int scsi_data_wait = SCSI_DATA_WAIT;
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int scsi_init_wait = SCSI_INIT_WAIT;
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int scsi_nosync = 1; /* inhibit sync xfers if 1 */
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int scsi_pridma = 0; /* use "priority" dma */
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#ifdef DEBUG
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int scsi_debug = 0;
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#define WAITHIST
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#endif
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#ifdef WAITHIST
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#define MAXWAIT 1022
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u_int ixstart_wait[MAXWAIT+2];
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u_int ixin_wait[MAXWAIT+2];
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u_int ixout_wait[MAXWAIT+2];
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u_int mxin_wait[MAXWAIT+2];
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u_int mxin2_wait[MAXWAIT+2];
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u_int cxin_wait[MAXWAIT+2];
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u_int fxfr_wait[MAXWAIT+2];
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u_int sgo_wait[MAXWAIT+2];
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#define HIST(h,w) (++h[((w)>MAXWAIT? MAXWAIT : ((w) < 0 ? -1 : (w))) + 1]);
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#else
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#define HIST(h,w)
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#endif
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#define b_cylin b_resid
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static void
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scsiabort(hs, hd, where)
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register struct scsi_softc *hs;
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volatile register struct scsidevice *hd;
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char *where;
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{
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int len;
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int maxtries; /* XXX - kludge till I understand whats *supposed* to happen */
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int startlen; /* XXX - kludge till I understand whats *supposed* to happen */
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u_char junk;
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printf("%s: abort from %s: phase=0x%x, ssts=0x%x, ints=0x%x\n",
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hs->sc_hc->hp_xname, where, hd->scsi_psns, hd->scsi_ssts,
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hd->scsi_ints);
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hd->scsi_ints = hd->scsi_ints;
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hd->scsi_csr = 0;
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if (hd->scsi_psns == 0 || (hd->scsi_ssts & SSTS_INITIATOR) == 0)
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/* no longer connected to scsi target */
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return;
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/* get the number of bytes remaining in current xfer + fudge */
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len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) | hd->scsi_tcl;
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/* for that many bus cycles, try to send an abort msg */
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for (startlen = (len += 1024); (hd->scsi_ssts & SSTS_INITIATOR) && --len >= 0; ) {
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hd->scsi_scmd = SCMD_SET_ATN;
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maxtries = 1000;
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while ((hd->scsi_psns & PSNS_REQ) == 0) {
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if (! (hd->scsi_ssts & SSTS_INITIATOR))
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goto out;
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DELAY(1);
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if (--maxtries == 0) {
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printf("-- scsiabort gave up after 1000 tries (startlen = %d len = %d)\n",
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startlen, len);
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goto out2;
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}
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}
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out2:
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if ((hd->scsi_psns & PHASE) == MESG_OUT_PHASE)
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hd->scsi_scmd = SCMD_RST_ATN;
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hd->scsi_pctl = hd->scsi_psns & PHASE;
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if (hd->scsi_psns & PHASE_IO) {
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/* one of the input phases - read & discard a byte */
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hd->scsi_scmd = SCMD_SET_ACK;
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if (hd->scsi_tmod == 0)
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while (hd->scsi_psns & PSNS_REQ)
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DELAY(1);
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junk = hd->scsi_temp;
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} else {
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/* one of the output phases - send an abort msg */
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hd->scsi_temp = MSG_ABORT;
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hd->scsi_scmd = SCMD_SET_ACK;
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if (hd->scsi_tmod == 0)
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while (hd->scsi_psns & PSNS_REQ)
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DELAY(1);
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}
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hd->scsi_scmd = SCMD_RST_ACK;
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}
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out:
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/*
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* Either the abort was successful & the bus is disconnected or
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* the device didn't listen. If the latter, announce the problem.
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* Either way, reset the card & the SPC.
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*/
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if (len < 0 && hs)
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printf("%s: abort failed. phase=0x%x, ssts=0x%x\n",
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hs->sc_hc->hp_xname, hd->scsi_psns, hd->scsi_ssts);
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if (! ((junk = hd->scsi_ints) & INTS_RESEL)) {
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hd->scsi_sctl |= SCTL_CTRLRST;
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DELAY(1);
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hd->scsi_sctl &=~ SCTL_CTRLRST;
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hd->scsi_hconf = 0;
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hd->scsi_ints = hd->scsi_ints;
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}
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}
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/*
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* XXX Set/reset long delays.
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*
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* if delay == 0, reset default delays
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* if delay < 0, set both delays to default long initialization values
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* if delay > 0, set both delays to this value
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*
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* Used when a devices is expected to respond slowly (e.g. during
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* initialization).
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*/
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void
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scsi_delay(delay)
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int delay;
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{
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static int saved_cmd_wait, saved_data_wait;
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if (delay) {
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saved_cmd_wait = scsi_cmd_wait;
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saved_data_wait = scsi_data_wait;
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if (delay > 0)
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scsi_cmd_wait = scsi_data_wait = delay;
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else
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scsi_cmd_wait = scsi_data_wait = scsi_init_wait;
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} else {
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scsi_cmd_wait = saved_cmd_wait;
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scsi_data_wait = saved_data_wait;
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}
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}
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int
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scsimatch(hc)
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register struct hp_ctlr *hc;
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{
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register struct scsi_softc *hs = &scsi_softc[hc->hp_unit];
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register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr;
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struct hp_hw *hw = hc->hp_args;
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/*
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* This is probably a little redundant, but what the heck.
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*/
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switch (hw->hw_id) {
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case 7:
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case 7+32:
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case 7+64:
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case 7+96:
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if ((hd->scsi_id & ID_MASK) != SCSI_ID)
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return (0);
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hc->hp_ipl = SCSI_IPL(hd->scsi_csr);
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return (1);
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/* NOTREACHED */
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}
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return (0);
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}
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void
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scsiattach(hc)
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struct hp_ctlr *hc;
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{
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register struct scsi_softc *hs = &scsi_softc[hc->hp_unit];
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register struct scsidevice *hd = (struct scsidevice *)hc->hp_addr;
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hs->sc_hc = hc;
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hs->sc_dq.dq_unit = hc->hp_unit;
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hs->sc_dq.dq_driver = &scsidriver;
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hs->sc_sq.dq_forw = hs->sc_sq.dq_back = &hs->sc_sq;
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/* Establish the interrupt handler. */
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isrlink(scsiintr, hs, hc->hp_ipl, ISRPRI_BIO);
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/* Reset the controller. */
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scsireset(hc->hp_unit);
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/*
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* Print information about what we've found.
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*/
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printf(":");
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if (hs->sc_flags & SCSI_DMA32)
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printf(" 32 bit dma, ");
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switch (hs->sc_sync) {
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case 0:
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printf("async");
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break;
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case (TMOD_SYNC | 0x3e):
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printf("250ns sync");
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break;
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case (TMOD_SYNC | 0x5e):
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printf("375ns sync");
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break;
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case (TMOD_SYNC | 0x7d):
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printf("500ns sync");
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break;
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default:
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panic("scsiattach: unknown sync param 0x%x", hs->sc_sync);
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}
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if ((hd->scsi_hconf & HCONF_PARITY) == 0)
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printf(", no parity");
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printf(", scsi id %d\n", hs->sc_scsiid);
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/*
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* XXX scale initialization wait according to CPU speed.
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* Should we do this for all wait? Should we do this at all?
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*/
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scsi_init_wait *= cpuspeed;
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}
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void
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scsireset(unit)
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register int unit;
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{
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register struct scsi_softc *hs = &scsi_softc[unit];
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volatile register struct scsidevice *hd =
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(struct scsidevice *)hs->sc_hc->hp_addr;
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u_int i;
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if (hs->sc_flags & SCSI_ALIVE)
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scsiabort(hs, hd, "reset");
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hd->scsi_id = 0xFF;
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DELAY(100);
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/*
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* Disable interrupts then reset the FUJI chip.
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*/
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hd->scsi_csr = 0;
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hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST;
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hd->scsi_scmd = 0;
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hd->scsi_tmod = 0;
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hd->scsi_pctl = 0;
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hd->scsi_temp = 0;
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hd->scsi_tch = 0;
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hd->scsi_tcm = 0;
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hd->scsi_tcl = 0;
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hd->scsi_ints = 0;
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if ((hd->scsi_id & ID_WORD_DMA) == 0)
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hs->sc_flags |= SCSI_DMA32;
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/* Determine Max Synchronous Transfer Rate */
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if (scsi_nosync)
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i = 3;
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else
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i = SCSI_SYNC_XFER(hd->scsi_hconf);
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switch (i) {
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case 0:
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hs->sc_sync = TMOD_SYNC | 0x3e; /* 250 nsecs */
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break;
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case 1:
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hs->sc_sync = TMOD_SYNC | 0x5e; /* 375 nsecs */
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break;
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case 2:
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hs->sc_sync = TMOD_SYNC | 0x7d; /* 500 nsecs */
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break;
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case 3:
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hs->sc_sync = 0;
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break;
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}
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/*
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* Configure the FUJI chip with its SCSI address, all
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* interrupts enabled & appropriate parity.
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*/
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i = (~hd->scsi_hconf) & 0x7;
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hs->sc_scsi_addr = 1 << i;
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hd->scsi_bdid = i;
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hs->sc_scsiid = i;
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if (hd->scsi_hconf & HCONF_PARITY)
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hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB |
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SCTL_SEL_ENAB | SCTL_RESEL_ENAB |
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SCTL_INTR_ENAB | SCTL_PARITY_ENAB;
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else
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hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB |
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SCTL_SEL_ENAB | SCTL_RESEL_ENAB |
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SCTL_INTR_ENAB;
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hd->scsi_sctl &=~ SCTL_DISABLE;
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hs->sc_flags |= SCSI_ALIVE;
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}
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static void
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scsierror(hs, hd, ints)
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register struct scsi_softc *hs;
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volatile register struct scsidevice *hd;
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u_char ints;
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{
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int unit = hs->sc_hc->hp_unit;
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char *sep = "";
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printf("%s: ", hs->sc_hc->hp_xname);
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if (ints & INTS_RST) {
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DELAY(100);
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if (hd->scsi_hconf & HCONF_SD)
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printf("spurious RST interrupt");
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else
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printf("hardware error - check fuse");
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sep = ", ";
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}
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if ((ints & INTS_HARD_ERR) || hd->scsi_serr) {
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if (hd->scsi_serr & SERR_SCSI_PAR) {
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printf("%sparity err", sep);
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sep = ", ";
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}
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if (hd->scsi_serr & SERR_SPC_PAR) {
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printf("%sSPC parity err", sep);
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sep = ", ";
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}
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if (hd->scsi_serr & SERR_TC_PAR) {
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printf("%sTC parity err", sep);
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sep = ", ";
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}
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if (hd->scsi_serr & SERR_PHASE_ERR) {
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printf("%sphase err", sep);
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sep = ", ";
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}
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if (hd->scsi_serr & SERR_SHORT_XFR) {
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printf("%ssync short transfer err", sep);
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sep = ", ";
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}
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if (hd->scsi_serr & SERR_OFFSET) {
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printf("%ssync offset error", sep);
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sep = ", ";
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}
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}
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if (ints & INTS_TIMEOUT)
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printf("%sSPC select timeout error", sep);
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if (ints & INTS_SRV_REQ)
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printf("%sspurious SRV_REQ interrupt", sep);
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if (ints & INTS_CMD_DONE)
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printf("%sspurious CMD_DONE interrupt", sep);
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if (ints & INTS_DISCON)
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printf("%sspurious disconnect interrupt", sep);
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if (ints & INTS_RESEL)
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printf("%sspurious reselect interrupt", sep);
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if (ints & INTS_SEL)
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printf("%sspurious select interrupt", sep);
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printf("\n");
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}
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static int
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issue_select(hd, target, our_addr)
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volatile register struct scsidevice *hd;
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u_char target, our_addr;
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{
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if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY))
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return (1);
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if (hd->scsi_ints & INTS_DISCON)
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hd->scsi_ints = INTS_DISCON;
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hd->scsi_pctl = 0;
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hd->scsi_temp = (1 << target) | our_addr;
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/* select timeout is hardcoded to 2ms */
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hd->scsi_tch = 0;
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hd->scsi_tcm = 32;
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hd->scsi_tcl = 4;
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hd->scsi_scmd = SCMD_SELECT;
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return (0);
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}
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static int
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wait_for_select(hd)
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volatile register struct scsidevice *hd;
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{
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u_char ints;
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while ((ints = hd->scsi_ints) == 0)
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DELAY(1);
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hd->scsi_ints = ints;
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return (!(hd->scsi_ssts & SSTS_INITIATOR));
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}
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static int
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ixfer_start(hd, len, phase, wait)
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volatile register struct scsidevice *hd;
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int len;
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u_char phase;
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register int wait;
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{
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hd->scsi_tch = len >> 16;
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hd->scsi_tcm = len >> 8;
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hd->scsi_tcl = len;
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hd->scsi_pctl = phase;
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hd->scsi_tmod = 0; /*XXX*/
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hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR;
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/* wait for xfer to start or svc_req interrupt */
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while ((hd->scsi_ssts & SSTS_BUSY) == 0) {
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if (hd->scsi_ints || --wait < 0) {
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#ifdef DEBUG
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if (scsi_debug)
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printf("ixfer_start fail: i%x, w%d\n",
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hd->scsi_ints, wait);
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#endif
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HIST(ixstart_wait, wait)
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return (0);
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}
|
|
DELAY(1);
|
|
}
|
|
HIST(ixstart_wait, wait)
|
|
return (1);
|
|
}
|
|
|
|
static int
|
|
ixfer_out(hd, len, buf)
|
|
volatile register struct scsidevice *hd;
|
|
int len;
|
|
register u_char *buf;
|
|
{
|
|
register int wait = scsi_data_wait;
|
|
|
|
for (; len > 0; --len) {
|
|
while (hd->scsi_ssts & SSTS_DREG_FULL) {
|
|
if (hd->scsi_ints || --wait < 0) {
|
|
#ifdef DEBUG
|
|
if (scsi_debug)
|
|
printf("ixfer_out fail: l%d i%x w%d\n",
|
|
len, hd->scsi_ints, wait);
|
|
#endif
|
|
HIST(ixout_wait, wait)
|
|
return (len);
|
|
}
|
|
DELAY(1);
|
|
}
|
|
hd->scsi_dreg = *buf++;
|
|
}
|
|
HIST(ixout_wait, wait)
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
ixfer_in(hd, len, buf)
|
|
volatile register struct scsidevice *hd;
|
|
int len;
|
|
register u_char *buf;
|
|
{
|
|
register int wait = scsi_data_wait;
|
|
|
|
for (; len > 0; --len) {
|
|
while (hd->scsi_ssts & SSTS_DREG_EMPTY) {
|
|
if (hd->scsi_ints || --wait < 0) {
|
|
while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) {
|
|
*buf++ = hd->scsi_dreg;
|
|
--len;
|
|
}
|
|
#ifdef DEBUG
|
|
if (scsi_debug)
|
|
printf("ixfer_in fail: l%d i%x w%d\n",
|
|
len, hd->scsi_ints, wait);
|
|
#endif
|
|
HIST(ixin_wait, wait)
|
|
return;
|
|
}
|
|
DELAY(1);
|
|
}
|
|
*buf++ = hd->scsi_dreg;
|
|
}
|
|
HIST(ixin_wait, wait)
|
|
}
|
|
|
|
static int
|
|
mxfer_in(hd, len, buf, phase)
|
|
volatile register struct scsidevice *hd;
|
|
register int len;
|
|
register u_char *buf;
|
|
register u_char phase;
|
|
{
|
|
register int wait = scsi_cmd_wait;
|
|
register int i;
|
|
|
|
hd->scsi_tmod = 0;
|
|
for (i = 0; i < len; ++i) {
|
|
/*
|
|
* manual sez: reset ATN before ACK is sent.
|
|
*/
|
|
if (hd->scsi_psns & PSNS_ATN)
|
|
hd->scsi_scmd = SCMD_RST_ATN;
|
|
/*
|
|
* wait for the request line (which says the target
|
|
* wants to give us data). If the phase changes while
|
|
* we're waiting, we're done.
|
|
*/
|
|
while ((hd->scsi_psns & PSNS_REQ) == 0) {
|
|
if (--wait < 0) {
|
|
HIST(mxin_wait, wait)
|
|
return (-1);
|
|
}
|
|
if ((hd->scsi_psns & PHASE) != phase ||
|
|
(hd->scsi_ssts & SSTS_INITIATOR) == 0)
|
|
goto out;
|
|
|
|
DELAY(1);
|
|
}
|
|
/*
|
|
* set ack (which says we're ready for the data, wait for
|
|
* req to go away (target says data is available), grab the
|
|
* data, then reset ack (say we've got the data).
|
|
*/
|
|
hd->scsi_pctl = phase;
|
|
hd->scsi_scmd = SCMD_SET_ACK;
|
|
while (hd->scsi_psns & PSNS_REQ) {
|
|
if (--wait < 0) {
|
|
HIST(mxin_wait, wait)
|
|
return (-2);
|
|
}
|
|
DELAY(1);
|
|
}
|
|
*buf++ = hd->scsi_temp;
|
|
hd->scsi_scmd = SCMD_RST_ACK;
|
|
}
|
|
out:
|
|
HIST(mxin_wait, wait)
|
|
/*
|
|
* Wait for manual transfer to finish.
|
|
* Avoids occasional "unexpected phase" errors in finishxfer
|
|
* formerly addressed by per-slave delays.
|
|
*/
|
|
wait = scsi_cmd_wait;
|
|
while ((hd->scsi_ssts & SSTS_ACTIVE) == SSTS_INITIATOR) {
|
|
if (--wait < 0)
|
|
break;
|
|
DELAY(1);
|
|
}
|
|
HIST(mxin2_wait, wait)
|
|
return (i);
|
|
}
|
|
|
|
/*
|
|
* SCSI 'immediate' command: issue a command to some SCSI device
|
|
* and get back an 'immediate' response (i.e., do programmed xfer
|
|
* to get the response data). 'cbuf' is a buffer containing a scsi
|
|
* command of length clen bytes. 'buf' is a buffer of length 'len'
|
|
* bytes for data. The transfer direction is determined by the device
|
|
* (i.e., by the scsi bus data xfer phase). If 'len' is zero, the
|
|
* command must supply no data. 'xferphase' is the bus phase the
|
|
* caller expects to happen after the command is issued. It should
|
|
* be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE.
|
|
*/
|
|
static int
|
|
scsiicmd(hs, target, cbuf, clen, buf, len, xferphase)
|
|
struct scsi_softc *hs;
|
|
int target;
|
|
u_char *cbuf;
|
|
int clen;
|
|
u_char *buf;
|
|
int len;
|
|
u_char xferphase;
|
|
{
|
|
volatile register struct scsidevice *hd =
|
|
(struct scsidevice *)hs->sc_hc->hp_addr;
|
|
u_char phase, ints;
|
|
register int wait;
|
|
|
|
/* select the SCSI bus (it's an error if bus isn't free) */
|
|
if (issue_select(hd, target, hs->sc_scsi_addr))
|
|
return (-1);
|
|
if (wait_for_select(hd))
|
|
return (-1);
|
|
/*
|
|
* Wait for a phase change (or error) then let the device
|
|
* sequence us through the various SCSI phases.
|
|
*/
|
|
hs->sc_stat[0] = 0xff;
|
|
hs->sc_msg[0] = 0xff;
|
|
phase = CMD_PHASE;
|
|
while (1) {
|
|
wait = scsi_cmd_wait;
|
|
switch (phase) {
|
|
|
|
case CMD_PHASE:
|
|
if (ixfer_start(hd, clen, phase, wait))
|
|
if (ixfer_out(hd, clen, cbuf))
|
|
goto abort;
|
|
phase = xferphase;
|
|
break;
|
|
|
|
case DATA_IN_PHASE:
|
|
if (len <= 0)
|
|
goto abort;
|
|
wait = scsi_data_wait;
|
|
if (ixfer_start(hd, len, phase, wait) ||
|
|
!(hd->scsi_ssts & SSTS_DREG_EMPTY))
|
|
ixfer_in(hd, len, buf);
|
|
phase = STATUS_PHASE;
|
|
break;
|
|
|
|
case DATA_OUT_PHASE:
|
|
if (len <= 0)
|
|
goto abort;
|
|
wait = scsi_data_wait;
|
|
if (ixfer_start(hd, len, phase, wait)) {
|
|
if (ixfer_out(hd, len, buf))
|
|
goto abort;
|
|
}
|
|
phase = STATUS_PHASE;
|
|
break;
|
|
|
|
case STATUS_PHASE:
|
|
wait = scsi_data_wait;
|
|
if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) ||
|
|
!(hd->scsi_ssts & SSTS_DREG_EMPTY))
|
|
ixfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat);
|
|
phase = MESG_IN_PHASE;
|
|
break;
|
|
|
|
case MESG_IN_PHASE:
|
|
if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) ||
|
|
!(hd->scsi_ssts & SSTS_DREG_EMPTY)) {
|
|
ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg);
|
|
hd->scsi_scmd = SCMD_RST_ACK;
|
|
}
|
|
phase = BUS_FREE_PHASE;
|
|
break;
|
|
|
|
case BUS_FREE_PHASE:
|
|
goto out;
|
|
|
|
default:
|
|
printf("%s: unexpected phase %d in icmd from %d\n",
|
|
hs->sc_hc->hp_xname, phase, target);
|
|
goto abort;
|
|
}
|
|
/* wait for last command to complete */
|
|
while ((ints = hd->scsi_ints) == 0) {
|
|
if (--wait < 0) {
|
|
HIST(cxin_wait, wait)
|
|
goto abort;
|
|
}
|
|
DELAY(1);
|
|
}
|
|
HIST(cxin_wait, wait)
|
|
hd->scsi_ints = ints;
|
|
if (ints & INTS_SRV_REQ)
|
|
phase = hd->scsi_psns & PHASE;
|
|
else if (ints & INTS_DISCON)
|
|
goto out;
|
|
else if ((ints & INTS_CMD_DONE) == 0) {
|
|
scsierror(hs, hd, ints);
|
|
goto abort;
|
|
}
|
|
}
|
|
abort:
|
|
scsiabort(hs, hd, "icmd");
|
|
out:
|
|
return (hs->sc_stat[0]);
|
|
}
|
|
|
|
/*
|
|
* Finish SCSI xfer command: After the completion interrupt from
|
|
* a read/write operation, sequence through the final phases in
|
|
* programmed i/o. This routine is a lot like scsiicmd except we
|
|
* skip (and don't allow) the select, cmd out and data in/out phases.
|
|
*/
|
|
static void
|
|
finishxfer(hs, hd, target)
|
|
struct scsi_softc *hs;
|
|
volatile register struct scsidevice *hd;
|
|
int target;
|
|
{
|
|
u_char phase, ints;
|
|
|
|
/*
|
|
* We specified padding xfer so we ended with either a phase
|
|
* change interrupt (normal case) or an error interrupt (handled
|
|
* elsewhere). Reset the board dma logic then try to get the
|
|
* completion status & command done msg. The reset confuses
|
|
* the SPC REQ/ACK logic so we have to do any status/msg input
|
|
* operations via 'manual xfer'.
|
|
*/
|
|
if (hd->scsi_ssts & SSTS_BUSY) {
|
|
int wait = scsi_cmd_wait;
|
|
|
|
/* wait for dma operation to finish */
|
|
while (hd->scsi_ssts & SSTS_BUSY) {
|
|
if (--wait < 0) {
|
|
#ifdef DEBUG
|
|
if (scsi_debug)
|
|
printf("finishxfer fail: ssts %x\n",
|
|
hd->scsi_ssts);
|
|
#endif
|
|
HIST(fxfr_wait, wait)
|
|
goto abort;
|
|
}
|
|
}
|
|
HIST(fxfr_wait, wait)
|
|
}
|
|
hd->scsi_scmd |= SCMD_PROG_XFR;
|
|
hd->scsi_sctl |= SCTL_CTRLRST;
|
|
DELAY(1);
|
|
hd->scsi_sctl &=~ SCTL_CTRLRST;
|
|
hd->scsi_hconf = 0;
|
|
/*
|
|
* The following delay is definitely needed when trying to
|
|
* write on a write protected disk (in the optical jukebox anyways),
|
|
* but we shall see if other unexplained machine freezeups
|
|
* also stop occuring... A value of 5 seems to work but
|
|
* 10 seems safer considering the potential consequences.
|
|
*/
|
|
DELAY(10);
|
|
hs->sc_stat[0] = 0xff;
|
|
hs->sc_msg[0] = 0xff;
|
|
hd->scsi_csr = 0;
|
|
hd->scsi_ints = ints = hd->scsi_ints;
|
|
while (1) {
|
|
phase = hd->scsi_psns & PHASE;
|
|
switch (phase) {
|
|
|
|
case STATUS_PHASE:
|
|
if (mxfer_in(hd, sizeof(hs->sc_stat), hs->sc_stat,
|
|
phase) <= 0)
|
|
goto abort;
|
|
break;
|
|
|
|
case MESG_IN_PHASE:
|
|
if (mxfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg,
|
|
phase) < 0)
|
|
goto abort;
|
|
break;
|
|
|
|
case BUS_FREE_PHASE:
|
|
return;
|
|
|
|
default:
|
|
printf("%s: unexpected phase %d in finishxfer from %d\n",
|
|
hs->sc_hc->hp_xname, phase, target);
|
|
goto abort;
|
|
}
|
|
if (ints = hd->scsi_ints) {
|
|
hd->scsi_ints = ints;
|
|
if (ints & INTS_DISCON)
|
|
return;
|
|
else if (ints & ~(INTS_SRV_REQ|INTS_CMD_DONE)) {
|
|
scsierror(hs, hd, ints);
|
|
break;
|
|
}
|
|
}
|
|
if ((hd->scsi_ssts & SSTS_INITIATOR) == 0)
|
|
return;
|
|
}
|
|
abort:
|
|
scsiabort(hs, hd, "finishxfer");
|
|
hs->sc_stat[0] = 0xfe;
|
|
}
|
|
|
|
int
|
|
scsi_test_unit_rdy(ctlr, slave, unit)
|
|
int ctlr, slave, unit;
|
|
{
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY };
|
|
|
|
cdb.lun = unit;
|
|
return (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0,
|
|
STATUS_PHASE));
|
|
}
|
|
|
|
int
|
|
scsi_request_sense(ctlr, slave, unit, buf, len)
|
|
int ctlr, slave, unit;
|
|
u_char *buf;
|
|
unsigned len;
|
|
{
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE };
|
|
|
|
cdb.lun = unit;
|
|
cdb.len = len;
|
|
return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE));
|
|
}
|
|
|
|
int
|
|
scsi_immed_command(ctlr, slave, unit, cdb, buf, len, rd)
|
|
int ctlr, slave, unit, rd;
|
|
struct scsi_fmt_cdb *cdb;
|
|
u_char *buf;
|
|
u_int len;
|
|
{
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
|
|
cdb->cdb[1] |= unit << 5;
|
|
return (scsiicmd(hs, slave, cdb->cdb, cdb->len, buf, len,
|
|
rd != 0? DATA_IN_PHASE : DATA_OUT_PHASE));
|
|
}
|
|
|
|
/*
|
|
* The following routines are test-and-transfer i/o versions of read/write
|
|
* for things like reading disk labels and writing core dumps. The
|
|
* routine scsigo should be used for normal data transfers, NOT these
|
|
* routines.
|
|
*/
|
|
int
|
|
scsi_tt_read(ctlr, slave, unit, buf, len, blk, bshift)
|
|
int ctlr, slave, unit;
|
|
u_char *buf;
|
|
u_int len;
|
|
daddr_t blk;
|
|
int bshift;
|
|
{
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
struct scsi_cdb10 cdb;
|
|
int stat;
|
|
int old_wait = scsi_data_wait;
|
|
|
|
scsi_data_wait = 300000;
|
|
bzero(&cdb, sizeof(cdb));
|
|
cdb.cmd = CMD_READ_EXT;
|
|
cdb.lun = unit;
|
|
blk >>= bshift;
|
|
cdb.lbah = blk >> 24;
|
|
cdb.lbahm = blk >> 16;
|
|
cdb.lbalm = blk >> 8;
|
|
cdb.lbal = blk;
|
|
cdb.lenh = len >> (8 + DEV_BSHIFT + bshift);
|
|
cdb.lenl = len >> (DEV_BSHIFT + bshift);
|
|
stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE);
|
|
scsi_data_wait = old_wait;
|
|
return (stat);
|
|
}
|
|
|
|
int
|
|
scsi_tt_write(ctlr, slave, unit, buf, len, blk, bshift)
|
|
int ctlr, slave, unit;
|
|
u_char *buf;
|
|
u_int len;
|
|
daddr_t blk;
|
|
int bshift;
|
|
{
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
struct scsi_cdb10 cdb;
|
|
int stat;
|
|
int old_wait = scsi_data_wait;
|
|
|
|
scsi_data_wait = 300000;
|
|
|
|
bzero(&cdb, sizeof(cdb));
|
|
cdb.cmd = CMD_WRITE_EXT;
|
|
cdb.lun = unit;
|
|
blk >>= bshift;
|
|
cdb.lbah = blk >> 24;
|
|
cdb.lbahm = blk >> 16;
|
|
cdb.lbalm = blk >> 8;
|
|
cdb.lbal = blk;
|
|
cdb.lenh = len >> (8 + DEV_BSHIFT + bshift);
|
|
cdb.lenl = len >> (DEV_BSHIFT + bshift);
|
|
stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE);
|
|
scsi_data_wait = old_wait;
|
|
return (stat);
|
|
}
|
|
|
|
int
|
|
scsireq(dq)
|
|
register struct devqueue *dq;
|
|
{
|
|
register struct devqueue *hq;
|
|
|
|
hq = &scsi_softc[dq->dq_ctlr].sc_sq;
|
|
insque(dq, hq->dq_back);
|
|
if (dq->dq_back == hq)
|
|
return(1);
|
|
return(0);
|
|
}
|
|
|
|
int
|
|
scsiustart(unit)
|
|
int unit;
|
|
{
|
|
register struct scsi_softc *hs = &scsi_softc[unit];
|
|
|
|
hs->sc_dq.dq_ctlr = DMA0 | DMA1;
|
|
hs->sc_flags |= SCSI_HAVEDMA;
|
|
if (dmareq(&hs->sc_dq))
|
|
return(1);
|
|
return(0);
|
|
}
|
|
|
|
void
|
|
scsistart(unit)
|
|
int unit;
|
|
{
|
|
register struct devqueue *dq;
|
|
|
|
dq = scsi_softc[unit].sc_sq.dq_forw;
|
|
(dq->dq_driver->d_go)(dq->dq_unit);
|
|
}
|
|
|
|
int
|
|
scsigo(ctlr, slave, unit, bp, cdb, pad)
|
|
int ctlr, slave, unit;
|
|
struct buf *bp;
|
|
struct scsi_fmt_cdb *cdb;
|
|
int pad;
|
|
{
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
volatile register struct scsidevice *hd =
|
|
(struct scsidevice *)hs->sc_hc->hp_addr;
|
|
int i, dmaflags;
|
|
u_char phase, ints, cmd;
|
|
|
|
cdb->cdb[1] |= unit << 5;
|
|
|
|
/* select the SCSI bus (it's an error if bus isn't free) */
|
|
if (issue_select(hd, slave, hs->sc_scsi_addr) || wait_for_select(hd)) {
|
|
if (hs->sc_flags & SCSI_HAVEDMA) {
|
|
hs->sc_flags &=~ SCSI_HAVEDMA;
|
|
dmafree(&hs->sc_dq);
|
|
}
|
|
return (1);
|
|
}
|
|
/*
|
|
* Wait for a phase change (or error) then let the device
|
|
* sequence us through command phase (we may have to take
|
|
* a msg in/out before doing the command). If the disk has
|
|
* to do a seek, it may be a long time until we get a change
|
|
* to data phase so, in the absense of an explicit phase
|
|
* change, we assume data phase will be coming up and tell
|
|
* the SPC to start a transfer whenever it does. We'll get
|
|
* a service required interrupt later if this assumption is
|
|
* wrong. Otherwise we'll get a service required int when
|
|
* the transfer changes to status phase.
|
|
*/
|
|
phase = CMD_PHASE;
|
|
while (1) {
|
|
register int wait = scsi_cmd_wait;
|
|
|
|
switch (phase) {
|
|
|
|
case CMD_PHASE:
|
|
if (ixfer_start(hd, cdb->len, phase, wait))
|
|
if (ixfer_out(hd, cdb->len, cdb->cdb))
|
|
goto abort;
|
|
break;
|
|
|
|
case MESG_IN_PHASE:
|
|
if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait)||
|
|
!(hd->scsi_ssts & SSTS_DREG_EMPTY)) {
|
|
ixfer_in(hd, sizeof(hs->sc_msg), hs->sc_msg);
|
|
hd->scsi_scmd = SCMD_RST_ACK;
|
|
}
|
|
phase = BUS_FREE_PHASE;
|
|
break;
|
|
|
|
case DATA_IN_PHASE:
|
|
case DATA_OUT_PHASE:
|
|
goto out;
|
|
|
|
default:
|
|
printf("%s: unexpected phase %d in go from %d\n",
|
|
hs->sc_hc->hp_xname, phase, slave);
|
|
goto abort;
|
|
}
|
|
while ((ints = hd->scsi_ints) == 0) {
|
|
if (--wait < 0) {
|
|
HIST(sgo_wait, wait)
|
|
goto abort;
|
|
}
|
|
DELAY(1);
|
|
}
|
|
HIST(sgo_wait, wait)
|
|
hd->scsi_ints = ints;
|
|
if (ints & INTS_SRV_REQ)
|
|
phase = hd->scsi_psns & PHASE;
|
|
else if (ints & INTS_CMD_DONE)
|
|
goto out;
|
|
else {
|
|
scsierror(hs, hd, ints);
|
|
goto abort;
|
|
}
|
|
}
|
|
out:
|
|
/*
|
|
* Reset the card dma logic, setup the dma channel then
|
|
* get the dio part of the card set for a dma xfer.
|
|
*/
|
|
hd->scsi_hconf = 0;
|
|
cmd = CSR_IE;
|
|
dmaflags = DMAGO_NOINT;
|
|
if (scsi_pridma)
|
|
dmaflags |= DMAGO_PRI;
|
|
if (bp->b_flags & B_READ)
|
|
dmaflags |= DMAGO_READ;
|
|
if ((hs->sc_flags & SCSI_DMA32) &&
|
|
((int)bp->b_un.b_addr & 3) == 0 && (bp->b_bcount & 3) == 0) {
|
|
cmd |= CSR_DMA32;
|
|
dmaflags |= DMAGO_LWORD;
|
|
} else
|
|
dmaflags |= DMAGO_WORD;
|
|
dmago(hs->sc_dq.dq_ctlr, bp->b_un.b_addr, bp->b_bcount, dmaflags);
|
|
|
|
if (bp->b_flags & B_READ) {
|
|
cmd |= CSR_DMAIN;
|
|
phase = DATA_IN_PHASE;
|
|
} else
|
|
phase = DATA_OUT_PHASE;
|
|
/*
|
|
* DMA enable bits must be set after size and direction bits.
|
|
*/
|
|
hd->scsi_csr = cmd;
|
|
hd->scsi_csr |= (CSR_DE0 << hs->sc_dq.dq_ctlr);
|
|
/*
|
|
* Setup the SPC for the transfer. We don't want to take
|
|
* first a command complete then a service required interrupt
|
|
* at the end of the transfer so we try to disable the cmd
|
|
* complete by setting the transfer counter to more bytes
|
|
* than we expect. (XXX - This strategy may have to be
|
|
* modified to deal with devices that return variable length
|
|
* blocks, e.g., some tape drives.)
|
|
*/
|
|
cmd = SCMD_XFR;
|
|
i = (unsigned)bp->b_bcount;
|
|
if (pad) {
|
|
cmd |= SCMD_PAD;
|
|
/*
|
|
* XXX - If we don't do this, the last 2 or 4 bytes
|
|
* (depending on word/lword DMA) of a read get trashed.
|
|
* It looks like it is necessary for the DMA to complete
|
|
* before the SPC goes into "pad mode"??? Note: if we
|
|
* also do this on a write, the request never completes.
|
|
*/
|
|
if (bp->b_flags & B_READ)
|
|
i += 2;
|
|
#ifdef DEBUG
|
|
hs->sc_flags |= SCSI_PAD;
|
|
if (i & 1)
|
|
printf("%s: odd byte count: %d bytes @ %d\n",
|
|
hs->sc_hc->hp_xname, i, bp->b_cylin);
|
|
#endif
|
|
} else
|
|
i += 4;
|
|
hd->scsi_tch = i >> 16;
|
|
hd->scsi_tcm = i >> 8;
|
|
hd->scsi_tcl = i;
|
|
hd->scsi_pctl = phase;
|
|
hd->scsi_tmod = 0;
|
|
hd->scsi_scmd = cmd;
|
|
hs->sc_flags |= SCSI_IO;
|
|
return (0);
|
|
abort:
|
|
scsiabort(hs, hd, "go");
|
|
hs->sc_flags &=~ SCSI_HAVEDMA;
|
|
dmafree(&hs->sc_dq);
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
scsidone(unit)
|
|
register int unit;
|
|
{
|
|
volatile register struct scsidevice *hd =
|
|
(struct scsidevice *)scsi_softc[unit].sc_hc->hp_addr;
|
|
|
|
#ifdef DEBUG
|
|
if (scsi_debug)
|
|
printf("%s: done called!\n", scsi_softc[unit].sc_hc->hp_xname);
|
|
#endif
|
|
/* dma operation is done -- turn off card dma */
|
|
hd->scsi_csr &=~ (CSR_DE1|CSR_DE0);
|
|
}
|
|
|
|
int
|
|
scsiintr(arg)
|
|
void *arg;
|
|
{
|
|
register struct scsi_softc *hs = arg;
|
|
volatile register struct scsidevice *hd =
|
|
(struct scsidevice *)hs->sc_hc->hp_addr;
|
|
register u_char ints;
|
|
register struct devqueue *dq;
|
|
int unit = hs->sc_hc->hp_unit;
|
|
|
|
if ((hd->scsi_csr & (CSR_IE|CSR_IR)) != (CSR_IE|CSR_IR))
|
|
return (0);
|
|
|
|
ints = hd->scsi_ints;
|
|
if ((ints & INTS_SRV_REQ) && (hs->sc_flags & SCSI_IO)) {
|
|
/*
|
|
* this should be the normal i/o completion case.
|
|
* get the status & cmd complete msg then let the
|
|
* device driver look at what happened.
|
|
*/
|
|
#ifdef DEBUG
|
|
int len = (hd->scsi_tch << 16) | (hd->scsi_tcm << 8) |
|
|
hd->scsi_tcl;
|
|
if (!(hs->sc_flags & SCSI_PAD))
|
|
len -= 4;
|
|
hs->sc_flags &=~ SCSI_PAD;
|
|
#endif
|
|
dq = hs->sc_sq.dq_forw;
|
|
finishxfer(hs, hd, dq->dq_slave);
|
|
hs->sc_flags &=~ (SCSI_IO|SCSI_HAVEDMA);
|
|
dmafree(&hs->sc_dq);
|
|
(dq->dq_driver->d_intr)(dq->dq_softc, hs->sc_stat[0]);
|
|
} else {
|
|
/* Something unexpected happened -- deal with it. */
|
|
hd->scsi_ints = ints;
|
|
hd->scsi_csr = 0;
|
|
scsierror(hs, hd, ints);
|
|
scsiabort(hs, hd, "intr");
|
|
if (hs->sc_flags & SCSI_IO) {
|
|
hs->sc_flags &=~ (SCSI_IO|SCSI_HAVEDMA);
|
|
dmafree(&hs->sc_dq);
|
|
dq = hs->sc_sq.dq_forw;
|
|
(dq->dq_driver->d_intr)(dq->dq_softc, -1);
|
|
}
|
|
}
|
|
return(1);
|
|
}
|
|
|
|
void
|
|
scsifree(dq)
|
|
register struct devqueue *dq;
|
|
{
|
|
register struct devqueue *hq;
|
|
|
|
hq = &scsi_softc[dq->dq_ctlr].sc_sq;
|
|
remque(dq);
|
|
if ((dq = hq->dq_forw) != hq)
|
|
(dq->dq_driver->d_start)(dq->dq_unit);
|
|
}
|
|
|
|
/*
|
|
* (XXX) The following routine is needed for the SCSI tape driver
|
|
* to read odd-size records.
|
|
*/
|
|
|
|
#include "st.h"
|
|
#if NST > 0
|
|
int
|
|
scsi_tt_oddio(ctlr, slave, unit, buf, len, b_flags, freedma)
|
|
int ctlr, slave, unit, b_flags, freedma;
|
|
u_char *buf;
|
|
u_int len;
|
|
{
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
struct scsi_cdb6 cdb;
|
|
u_char iphase;
|
|
int stat;
|
|
|
|
#ifdef DEBUG
|
|
if (freedma && (hs->sc_flags & SCSI_HAVEDMA) == 0 ||
|
|
!freedma && (hs->sc_flags & SCSI_HAVEDMA))
|
|
printf("oddio: freedma (%d) inconsistency (flags=%x)\n",
|
|
freedma, hs->sc_flags);
|
|
#endif
|
|
/*
|
|
* First free any DMA channel that was allocated.
|
|
* We can't use DMA to do this transfer.
|
|
*/
|
|
if (freedma) {
|
|
hs->sc_flags &=~ SCSI_HAVEDMA;
|
|
dmafree(hs->sc_dq);
|
|
}
|
|
/*
|
|
* Initialize command block
|
|
*/
|
|
bzero(&cdb, sizeof(cdb));
|
|
cdb.lun = unit;
|
|
cdb.lbam = (len >> 16) & 0xff;
|
|
cdb.lbal = (len >> 8) & 0xff;
|
|
cdb.len = len & 0xff;
|
|
if (buf == 0) {
|
|
cdb.cmd = CMD_SPACE;
|
|
cdb.lun |= 0x00;
|
|
len = 0;
|
|
iphase = MESG_IN_PHASE;
|
|
} else if (b_flags & B_READ) {
|
|
cdb.cmd = CMD_READ;
|
|
iphase = DATA_IN_PHASE;
|
|
} else {
|
|
cdb.cmd = CMD_WRITE;
|
|
iphase = DATA_OUT_PHASE;
|
|
}
|
|
/*
|
|
* Perform command (with very long delays)
|
|
*/
|
|
scsi_delay(30000000);
|
|
stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, iphase);
|
|
scsi_delay(0);
|
|
return (stat);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Copy a counted string, trimming the trailing space, and turn
|
|
* the result into a C-style string.
|
|
*/
|
|
void
|
|
scsi_str(src, dst, len)
|
|
char *src, *dst;
|
|
size_t len;
|
|
{
|
|
|
|
while (src[len - 1] == ' ') {
|
|
if (--len == 0) {
|
|
*dst = '\0';
|
|
return;
|
|
}
|
|
}
|
|
bcopy(src, dst, len);
|
|
dst[len] = '\0';
|
|
}
|
|
#endif
|