535 lines
15 KiB
C
535 lines
15 KiB
C
/* $NetBSD: asc_tcds.c,v 1.1 2000/07/04 02:22:19 nisimura Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: asc_tcds.c,v 1.1 2000/07/04 02:22:19 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <machine/bus.h>
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#include <dev/tc/tcvar.h>
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#include <dev/tc/tcdsreg.h>
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#include <dev/tc/tcdsvar.h>
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struct asc_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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bus_space_tag_t sc_bst; /* bus space tag */
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bus_space_handle_t sc_scsi_bsh; /* ASC register handle */
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bus_dma_tag_t sc_dmat; /* bus dma tag */
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bus_dmamap_t sc_dmamap; /* bus dmamap */
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caddr_t *sc_dmaaddr;
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size_t *sc_dmalen;
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size_t sc_dmasize;
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unsigned sc_flags;
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#define ASC_ISPULLUP 0x01
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#define ASC_DMAACTIVE 0x02
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#define ASC_MAPLOADED 0x04
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struct tcds_slotconfig *sc_tcds; /* DMA/slot info lives here */
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};
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static int asc_tcds_match __P((struct device *, struct cfdata *, void *));
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static void asc_tcds_attach __P((struct device *, struct device *, void *));
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/* Linkup to the rest of the kernel */
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struct cfattach asc_tcds_ca = {
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sizeof(struct asc_softc), asc_tcds_match, asc_tcds_attach
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};
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/*
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* Functions and the switch for the MI code.
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*/
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static u_char asc_read_reg __P((struct ncr53c9x_softc *, int));
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static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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static int tcds_dma_isintr __P((struct ncr53c9x_softc *));
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static void tcds_dma_reset __P((struct ncr53c9x_softc *));
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static int tcds_dma_intr __P((struct ncr53c9x_softc *));
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static int tcds_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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static void tcds_dma_go __P((struct ncr53c9x_softc *));
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static void tcds_dma_stop __P((struct ncr53c9x_softc *));
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static int tcds_dma_isactive __P((struct ncr53c9x_softc *));
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static void tcds_clear_latched_intr __P((struct ncr53c9x_softc *));
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static struct ncr53c9x_glue asc_tcds_glue = {
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asc_read_reg,
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asc_write_reg,
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tcds_dma_isintr,
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tcds_dma_reset,
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tcds_dma_intr,
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tcds_dma_setup,
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tcds_dma_go,
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tcds_dma_stop,
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tcds_dma_isactive,
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tcds_clear_latched_intr,
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};
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static int
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asc_tcds_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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/* We always exist. */
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return 1;
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}
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#define DMAMAX(a) (NBPG - ((a) & (NBPG - 1)))
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/*
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* Attach this instance, and then all the sub-devices
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*/
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static void
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asc_tcds_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct tcdsdev_attach_args *tcdsdev = aux;
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struct asc_softc *asc = (struct asc_softc *)self;
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struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x;
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int error;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &asc_tcds_glue;
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asc->sc_bst = tcdsdev->tcdsda_bst;
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asc->sc_scsi_bsh = tcdsdev->tcdsda_bsh;
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asc->sc_tcds = tcdsdev->tcdsda_sc;
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/*
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* The TCDS ASIC cannot DMA across 8k boundaries, and this
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* driver is written such that each DMA segment gets a new
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* call to tcds_dma_setup(). Thus, the DMA map only needs
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* to support 8k transfers.
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*/
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asc->sc_dmat = tcdsdev->tcdsda_dmat;
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if ((error = bus_dmamap_create(asc->sc_dmat, NBPG, 1, NBPG,
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NBPG, BUS_DMA_NOWAIT, &asc->sc_dmamap)) < 0) {
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printf("failed to create dma map, error = %d\n", error);
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}
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sc->sc_id = tcdsdev->tcdsda_id;
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sc->sc_freq = tcdsdev->tcdsda_freq;
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/* gimme Mhz */
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sc->sc_freq /= 1000000;
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tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc);
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* Set up static configuration info.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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sc->sc_cfg3 = NCRCFG3_CDB;
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if (sc->sc_freq > 25)
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sc->sc_cfg3 |= NCRF9XCFG3_FCLK;
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sc->sc_rev = tcdsdev->tcdsda_variant;
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if (tcdsdev->tcdsda_fast) {
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sc->sc_features |= NCR_F_FASTSCSI;
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sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI;
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}
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4;
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sc->sc_maxxfer = 64 * 1024;
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/* Do the common parts of attachment. */
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ncr53c9x_attach(sc, NULL, NULL);
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}
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static void
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tcds_dma_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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/* TCDS SCSI disable/reset/enable. */
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tcds_scsi_reset(asc->sc_tcds); /* XXX */
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if (asc->sc_flags & ASC_MAPLOADED)
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bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
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asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
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}
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/*
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* start a dma transfer or keep it going
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*/
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int
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tcds_dma_setup(sc, addr, len, ispullup, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len, *dmasize;
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int ispullup; /* DMA into main memory */
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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struct tcds_slotconfig *tcds = asc->sc_tcds;
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size_t size;
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u_int32_t dic;
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NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot,
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(int)*asc->sc_dmalen, *asc->sc_dmaaddr,
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(ispullup) ? "IN" : "OUT"));
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/*
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* the rules say we cannot transfer more than the limit
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* of this DMA chip (64k) and we cannot cross a 8k boundary.
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*/
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size = min(*dmasize, DMAMAX((size_t)*addr));
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asc->sc_dmaaddr = addr;
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asc->sc_dmalen = len;
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asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0;
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*dmasize = asc->sc_dmasize = size;
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NCR_DMA(("dma_start: dmasize = %d\n", (int)size));
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if (size == 0)
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return 0;
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if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, size,
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NULL, BUS_DMA_NOWAIT)) {
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/*
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* XXX Should return an error, here, but the upper-layer
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* XXX doesn't check the return value!
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*/
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panic("tcds_dma_setup: dmamap load failed");
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}
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/* synchronize dmamap contents with memory image */
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bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 0, size,
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(ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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/* load address, set/clear unaligned transfer and read/write bits. */
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bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda,
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asc->sc_dmamap->dm_segs[0].ds_addr >> 2);
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dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic);
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dic &= ~TCDS_DIC_ADDRMASK;
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dic |= asc->sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK;
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if (ispullup)
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dic |= TCDS_DIC_WRITE;
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else
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dic &= ~TCDS_DIC_WRITE;
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bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic);
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asc->sc_flags |= ASC_MAPLOADED;
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return 0;
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}
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static void
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tcds_dma_go(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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/* mark unit as DMA-active */
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asc->sc_flags |= ASC_DMAACTIVE;
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/* start DMA */
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tcds_dma_enable(asc->sc_tcds, 1);
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}
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static void
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tcds_dma_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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#if 0
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struct asc_softc *asc = (struct asc_softc *)sc;
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#endif
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/*
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* XXX STOP DMA HERE!
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*/
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}
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/*
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* Pseudo (chained) interrupt from the asc driver to kick the
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* current running DMA transfer. Called from ncr53c9x_intr()
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* for now.
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*
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* return 1 if it was a DMA continue.
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*/
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static int
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tcds_dma_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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struct tcds_slotconfig *tcds = asc->sc_tcds;
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int trans, resid;
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u_int32_t tcl, tcm;
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u_int32_t dud, dudmask, *addr;
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bus_addr_t pa;
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NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot));
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if (tcds_scsi_iserr(tcds))
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return 0;
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/* This is an "assertion" :) */
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if ((asc->sc_flags & ASC_DMAACTIVE) == 0)
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panic("tcds_dma_intr: DMA wasn't active");
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/* DMA has stopped */
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tcds_dma_enable(tcds, 0);
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asc->sc_flags &= ~ASC_DMAACTIVE;
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if (asc->sc_dmasize == 0) {
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/* A "Transfer Pad" operation completed */
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tcl = NCR_READ_REG(sc, NCR_TCL);
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tcm = NCR_READ_REG(sc, NCR_TCM);
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NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n",
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tcl | (tcm << 8), tcl, tcm));
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return 0;
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}
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resid = 0;
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if ((asc->sc_flags & ASC_ISPULLUP) == 0 &&
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(resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid));
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DELAY(1);
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}
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resid += (tcl = NCR_READ_REG(sc, NCR_TCL));
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resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8;
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trans = asc->sc_dmasize - resid;
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if (trans < 0) { /* transferred < 0 ? */
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printf("tcds_dma %d: xfer (%d) > req (%d)\n",
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tcds->sc_slot, trans, (int)asc->sc_dmasize);
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trans = asc->sc_dmasize;
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}
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NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n",
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tcl, tcm, trans, resid));
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*asc->sc_dmalen -= trans;
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*asc->sc_dmaaddr += trans;
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bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
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0, asc->sc_dmamap->dm_mapsize,
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(sc->sc_flags & ASC_ISPULLUP)
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? BUS_DMASYNC_POSTREAD
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: BUS_DMASYNC_POSTWRITE);
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/*
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* Clean up unaligned DMAs into main memory.
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*/
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if (asc->sc_flags & ASC_ISPULLUP) {
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/* Handle unaligned starting address, length. */
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dud = bus_space_read_4(tcds->sc_bst,
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tcds->sc_bsh, tcds->sc_dud0);
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if ((dud & TCDS_DUD0_VALIDBITS) != 0) {
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addr = (u_int32_t *)
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((paddr_t)*asc->sc_dmaaddr & ~0x3);
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dudmask = 0;
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if (dud & TCDS_DUD0_VALID00)
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panic("tcds_dma: dud0 byte 0 valid");
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if (dud & TCDS_DUD0_VALID01)
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dudmask |= TCDS_DUD_BYTE01;
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if (dud & TCDS_DUD0_VALID10)
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dudmask |= TCDS_DUD_BYTE10;
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#ifdef DIAGNOSTIC
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if (dud & TCDS_DUD0_VALID11)
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dudmask |= TCDS_DUD_BYTE11;
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#endif
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NCR_DMA(("dud0 at 0x%p dudmask 0x%x\n",
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addr, dudmask));
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*addr = (*addr & ~dudmask) | (dud & dudmask);
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}
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dud = bus_space_read_4(tcds->sc_bst,
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tcds->sc_bsh, tcds->sc_dud1);
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if ((dud & TCDS_DUD1_VALIDBITS) != 0) {
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pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh,
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tcds->sc_sda) << 2;
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dudmask = 0;
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if (dud & TCDS_DUD1_VALID00)
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dudmask |= TCDS_DUD_BYTE00;
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if (dud & TCDS_DUD1_VALID01)
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dudmask |= TCDS_DUD_BYTE01;
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if (dud & TCDS_DUD1_VALID10)
|
|
dudmask |= TCDS_DUD_BYTE10;
|
|
#ifdef DIAGNOSTIC
|
|
if (dud & TCDS_DUD1_VALID11)
|
|
panic("tcds_dma: dud1 byte 3 valid");
|
|
#endif
|
|
NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n",
|
|
pa, dudmask));
|
|
/* XXX Fix TC_PHYS_TO_UNCACHED() */
|
|
#if defined(__alpha__)
|
|
addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa);
|
|
#elif defined(__mips__)
|
|
addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa);
|
|
#else
|
|
#error TURBOchannel only exists on DECs, folks...
|
|
#endif
|
|
*addr = (*addr & ~dudmask) | (dud & dudmask);
|
|
}
|
|
/* XXX deal with saved residual byte? */
|
|
}
|
|
|
|
bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
|
|
asc->sc_flags &= ~ASC_MAPLOADED;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Glue functions.
|
|
*/
|
|
static u_char
|
|
asc_read_reg(sc, reg)
|
|
struct ncr53c9x_softc *sc;
|
|
int reg;
|
|
{
|
|
struct asc_softc *asc = (struct asc_softc *)sc;
|
|
u_int32_t v;
|
|
|
|
v = bus_space_read_4(asc->sc_bst, asc->sc_scsi_bsh,
|
|
reg * sizeof(u_int32_t));
|
|
|
|
return v & 0xff;
|
|
}
|
|
|
|
static void
|
|
asc_write_reg(sc, reg, val)
|
|
struct ncr53c9x_softc *sc;
|
|
int reg;
|
|
u_char val;
|
|
{
|
|
struct asc_softc *asc = (struct asc_softc *)sc;
|
|
|
|
bus_space_write_4(asc->sc_bst, asc->sc_scsi_bsh,
|
|
reg * sizeof(u_int32_t), val);
|
|
}
|
|
|
|
static int
|
|
tcds_dma_isintr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct asc_softc *asc = (struct asc_softc *)sc;
|
|
int x;
|
|
|
|
x = tcds_scsi_isintr(asc->sc_tcds, 1);
|
|
|
|
/* XXX */
|
|
return x;
|
|
}
|
|
|
|
static int
|
|
tcds_dma_isactive(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct asc_softc *asc = (struct asc_softc *)sc;
|
|
|
|
return !!(asc->sc_flags & ASC_DMAACTIVE);
|
|
}
|
|
|
|
static void
|
|
tcds_clear_latched_intr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct asc_softc *asc = (struct asc_softc *)sc;
|
|
|
|
/* Clear the TCDS interrupt bit. */
|
|
(void)tcds_scsi_isintr(asc->sc_tcds, 1);
|
|
}
|