325 lines
9.1 KiB
C
325 lines
9.1 KiB
C
/* $NetBSD: pci_gio.c,v 1.5 2007/02/19 04:48:37 rumble Exp $ */
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/*
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* Copyright (c) 2006 Stephen M. Rumble
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.5 2007/02/19 04:48:37 rumble Exp $");
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/*
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* Glue for PCI devices that are connected to the GIO bus by various little
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* GIO<->PCI ASICs.
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*
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* We presently support the following boards:
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* o Phobos G100/G130/G160 (if_tlp, lxtphy)
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* o Set Engineering GFE (if_tl, nsphy)
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*/
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#include "opt_pci.h"
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#include "pci.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/extent.h>
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#include <machine/bus.h>
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#include <machine/machtype.h>
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#include <sgimips/gio/giovar.h>
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#include <sgimips/gio/gioreg.h>
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#include <sgimips/gio/giodevs.h>
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#include <sgimips/dev/imcvar.h>
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#include <mips/cache.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciconf.h>
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int giopci_debug = 0;
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#define DPRINTF(_x) if (giopci_debug) printf _x
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struct giopci_softc {
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struct device sc_dev;
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struct sgimips_pci_chipset sc_pc;
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int sc_slot;
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int sc_gprid;
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uint32_t sc_pci_len;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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};
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static int giopci_match(struct device *, struct cfdata *, void *);
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static void giopci_attach(struct device *, struct device *, void *);
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static int giopci_bus_maxdevs(pci_chipset_tag_t, int);
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static pcireg_t giopci_conf_read(pci_chipset_tag_t, pcitag_t, int);
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static void giopci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
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static int giopci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t);
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static int giopci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
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static const char *
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giopci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
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static void *giopci_intr_establish(int, int, int (*)(void *), void *);
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static void giopci_intr_disestablish(void *);
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#define PHOBOS_PCI_OFFSET 0x00100000
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#define PHOBOS_PCI_LENGTH 128 /* ~arbitrary */
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#define PHOBOS_TULIP_START 0x00101000
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#define PHOBOS_TULIP_END 0x001fffff
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#define SETENG_MAGIC_OFFSET 0x00020000
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#define SETENG_MAGIC_VALUE 0x00001000
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#define SETENG_PCI_OFFSET 0x00080000
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#define SETENG_PCI_LENGTH 128 /* ~arbitrary */
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#define SETENG_TLAN_START 0x00100000
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#define SETENG_TLAN_END 0x001fffff
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CFATTACH_DECL(giopci, sizeof(struct giopci_softc),
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giopci_match, giopci_attach, NULL, NULL);
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static int
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giopci_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct gio_attach_args *ga = aux;
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int gprid;
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/*
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* I think that these cards are all GIO32-bis or GIO64. Thus
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* they work in either Indigo2/Challenge M or
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* Indy/Challenge S/Indigo R4k, according to form factor. However,
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* there are some exceptions (e.g. my Indigo R4k won't power
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* on with the Set Engineering card installed).
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*/
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if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
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return (0);
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gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
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if (gprid == PHOBOS_G100 || gprid == PHOBOS_G130 ||
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gprid == PHOBOS_G160 || gprid == SETENG_GFE)
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return (1);
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return (0);
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}
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static void
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giopci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct giopci_softc *sc = (void *)self;
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pci_chipset_tag_t pc = &sc->sc_pc;
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struct gio_attach_args *ga = aux;
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uint32_t pci_off, pci_len, arb;
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struct pcibus_attach_args pba;
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u_long m_start, m_end;
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#ifdef PCI_NETBSD_CONFIGURE
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extern int pci_conf_debug;
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pci_conf_debug = giopci_debug;
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#endif
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sc->sc_iot = ga->ga_iot;
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sc->sc_slot = ga->ga_slot;
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sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
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if (mach_type == MACH_SGI_IP22 &&
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mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE;
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else
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arb = GIO_ARB_RT | GIO_ARB_MST;
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if (gio_arb_config(ga->ga_slot, arb)) {
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printf(": failed to configure GIO bus arbiter\n");
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return;
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}
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#if (NIMC > 0)
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imc_disable_sysad_parity();
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#endif
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switch (sc->sc_gprid) {
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case PHOBOS_G100:
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case PHOBOS_G130:
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case PHOBOS_G160:
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pci_off = PHOBOS_PCI_OFFSET;
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pci_len = PHOBOS_PCI_LENGTH;
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m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START);
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m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END);
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break;
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case SETENG_GFE:
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/*
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* NB: The SetEng board does not allow the ThunderLAN's DMA
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* engine to properly transfer segments that span page
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* boundaries. See sgimips/autoconf.c where we catch a
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* tl(4) device attachment and create an appropriate
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* proplib entry to enable the workaround.
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*/
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pci_off = SETENG_PCI_OFFSET;
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pci_len = SETENG_PCI_LENGTH;
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m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START);
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m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END);
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bus_space_write_4(ga->ga_iot, ga->ga_ioh,
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SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE);
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break;
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default:
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panic("giopci_attach: unsupported GIO product id 0x%02x",
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sc->sc_gprid);
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}
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if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len,
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&sc->sc_ioh)) {
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printf("%s: unable to map PCI registers\n",sc->sc_dev.dv_xname);
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return;
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}
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sc->sc_pci_len = pci_len;
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pc->pc_bus_maxdevs = giopci_bus_maxdevs;
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pc->pc_conf_read = giopci_conf_read;
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pc->pc_conf_write = giopci_conf_write;
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pc->pc_conf_hook = giopci_conf_hook;
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pc->pc_intr_map = giopci_intr_map;
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pc->pc_intr_string = giopci_intr_string;
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pc->intr_establish = giopci_intr_establish;
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pc->intr_disestablish = giopci_intr_disestablish;
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pc->iot = ga->ga_iot;
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pc->ioh = ga->ga_ioh;
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pc->cookie = sc;
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printf(": %s\n", gio_product_string(sc->sc_gprid));
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#ifdef PCI_NETBSD_CONFIGURE
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pc->pc_memext = extent_create("giopcimem", m_start, m_end,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0, mips_dcache_align);
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#endif
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memset(&pba, 0, sizeof(pba));
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pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
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pba.pba_dmat = ga->ga_dmat;
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pba.pba_pc = pc;
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pba.pba_flags = PCI_FLAGS_MEM_ENABLED;
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/* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */
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config_found_ia(self, "pcibus", &pba, pcibusprint);
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}
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static int
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giopci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
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{
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return (busno == 0);
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}
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static pcireg_t
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giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
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{
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struct giopci_softc *sc = pc->cookie;
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int bus, dev, func;
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pcireg_t data;
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pci_decompose_tag(pc, tag, &bus, &dev, &func);
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if (bus != 0 || dev != 0 || func != 0)
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return (0);
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/* XXX - should just use bus_space_peek */
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if (reg >= sc->sc_pci_len) {
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DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg));
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return (0);
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}
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DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg));
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data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
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DPRINTF(("%08x\n", data));
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return (data);
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}
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static void
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giopci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
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{
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struct giopci_softc *sc = pc->cookie;
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int bus, dev, func;
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pci_decompose_tag(pc, tag, &bus, &dev, &func);
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if (bus != 0 || dev != 0 || func != 0)
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return;
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/* XXX - should just use bus_space_poke */
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if (reg >= sc->sc_pci_len) {
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DPRINTF(("giopci_conf_write: reg 0x%x out of bounds "
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"(val = 0x%08x)\n", reg, data));
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return;
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}
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DPRINTF(("giopci_conf_write: reg 0x%x = 0x%08x\n", reg, data));
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data);
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}
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static int
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giopci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function,
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pcireg_t id)
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{
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/* All devices use memory accesses only. */
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return (PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM);
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}
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static int
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giopci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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struct giopci_softc *sc = pa->pa_pc->cookie;
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*ihp = sc->sc_slot;
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return (0);
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}
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static const char *
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giopci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
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{
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static char str[10];
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snprintf(str, sizeof(str), "slot %s",
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(ih == GIO_SLOT_EXP0) ? "EXP0" :
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(ih == GIO_SLOT_EXP1) ? "EXP1" : "GFX");
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return (str);
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}
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static void *
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giopci_intr_establish(int slot, int level, int (*func)(void *), void *arg)
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{
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return (gio_intr_establish(slot, level, func, arg));
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}
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static void
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giopci_intr_disestablish(void *cookie)
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{
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panic("giopci_intr_disestablish: impossible.");
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}
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