173 lines
6.9 KiB
C
173 lines
6.9 KiB
C
/* $NetBSD: if_lereg.h,v 1.4 2005/12/11 12:18:19 christos Exp $ */
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/*-
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* Copyright (c) 1982, 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)if_lereg.h 8.2 (Berkeley) 10/30/93
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*/
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#define LEMTU 1518
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#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
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#define LERBUF 8
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#define LERBUFLOG2 3
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#define LE_RLEN (LERBUFLOG2 << 13)
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#define LETBUF 1
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#define LETBUFLOG2 0
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#define LE_TLEN (LETBUFLOG2 << 13)
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/* Local Area Network Controller for Ethernet (LANCE) registers */
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struct lereg1 {
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volatile u_short ler1_rdp; /* register data port */
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volatile u_short ler1_rap; /* register address port */
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};
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/* register addresses */
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#define LE_CSR0 0 /* Control and status register */
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#define LE_CSR1 1 /* low address of init block */
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#define LE_CSR2 2 /* high address of init block */
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#define LE_CSR3 3 /* Bus master and control */
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/* Control and status register 0 (csr0) */
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#define LE_C0_ERR 0x8000 /* error summary */
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#define LE_C0_BABL 0x4000 /* transmitter timeout error */
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#define LE_C0_CERR 0x2000 /* collision */
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#define LE_C0_MISS 0x1000 /* missed a packet */
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#define LE_C0_MERR 0x0800 /* memory error */
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#define LE_C0_RINT 0x0400 /* receiver interrupt */
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#define LE_C0_TINT 0x0200 /* transmitter interrupt */
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#define LE_C0_IDON 0x0100 /* initialization done */
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#define LE_C0_INTR 0x0080 /* interrupt condition */
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#define LE_C0_INEA 0x0040 /* interrupt enable */
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#define LE_C0_RXON 0x0020 /* receiver on */
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#define LE_C0_TXON 0x0010 /* transmitter on */
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#define LE_C0_TDMD 0x0008 /* transmit demand */
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#define LE_C0_STOP 0x0004 /* disable all external activity */
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#define LE_C0_STRT 0x0002 /* enable external activity */
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#define LE_C0_INIT 0x0001 /* begin initialization */
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#define LE_C0_BITS \
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"\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
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\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
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/* Control and status register 3 (csr3) */
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#define LE_C3_BSWP 0x4 /* byte swap */
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#define LE_C3_ACON 0x2 /* ALE control, eh? */
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#define LE_C3_BCON 0x1 /* byte control */
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/*
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* Current size is 13,758 bytes with 8 x 1518 receive buffers and
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* 1 x 1518 transmit buffer.
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*/
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struct lereg2 {
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/* initialization block */
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volatile u_short ler2_mode; /* mode */
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volatile u_char ler2_padr[6]; /* physical address */
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#ifdef new_code
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volatile u_short ler2_ladrf[4]; /* logical address filter */
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#else
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volatile u_long ler2_ladrf0; /* logical address filter */
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volatile u_long ler2_ladrf1; /* logical address filter */
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#endif
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volatile u_short ler2_rdra; /* receive descriptor addr */
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volatile u_short ler2_rlen; /* rda high and ring size */
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volatile u_short ler2_tdra; /* transmit descriptor addr */
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volatile u_short ler2_tlen; /* tda high and ring size */
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/* receive message descriptors. bits/hadr are byte order dependent. */
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struct lermd {
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volatile u_short rmd0; /* low address of packet */
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volatile u_char rmd1_bits; /* descriptor bits */
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volatile u_char rmd1_hadr; /* high address of packet */
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volatile short rmd2; /* buffer byte count */
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volatile u_short rmd3; /* message byte count */
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} ler2_rmd[LERBUF];
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/* transmit message descriptors */
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struct letmd {
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volatile u_short tmd0; /* low address of packet */
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volatile u_char tmd1_bits; /* descriptor bits */
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volatile u_char tmd1_hadr; /* high address of packet */
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volatile short tmd2; /* buffer byte count */
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volatile u_short tmd3; /* transmit error bits */
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} ler2_tmd[LETBUF];
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volatile char ler2_rbuf[LERBUF][LEMTU];
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volatile char ler2_tbuf[LETBUF][LEMTU];
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};
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/* Initialzation block (mode) */
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#define LE_MODE_PROM 0x8000 /* promiscuous mode */
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/* 0x7f80 reserved, must be zero */
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#define LE_MODE_INTL 0x0040 /* internal loopback */
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#define LE_MODE_DRTY 0x0020 /* disable retry */
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#define LE_MODE_COLL 0x0010 /* force a collision */
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#define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
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#define LE_MODE_LOOP 0x0004 /* loopback mode */
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#define LE_MODE_DTX 0x0002 /* disable transmitter */
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#define LE_MODE_DRX 0x0001 /* disable receiver */
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#define LE_MODE_NORMAL 0 /* none of the above */
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/* Receive message descriptor 1 (rmd1_bits) */
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#define LE_R1_OWN 0x80 /* LANCE owns the packet */
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#define LE_R1_ERR 0x40 /* error summary */
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#define LE_R1_FRAM 0x20 /* framing error */
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#define LE_R1_OFLO 0x10 /* overflow error */
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#define LE_R1_CRC 0x08 /* CRC error */
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#define LE_R1_BUFF 0x04 /* buffer error */
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#define LE_R1_STP 0x02 /* start of packet */
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#define LE_R1_ENP 0x01 /* end of packet */
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#define LE_R1_BITS \
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"\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
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/* Transmit message descriptor 1 (tmd1_bits) */
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#define LE_T1_OWN 0x80 /* LANCE owns the packet */
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#define LE_T1_ERR 0x40 /* error summary */
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#define LE_T1_MORE 0x10 /* multiple collisions */
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#define LE_T1_ONE 0x08 /* single collision */
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#define LE_T1_DEF 0x04 /* defferred transmit */
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#define LE_T1_STP 0x02 /* start of packet */
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#define LE_T1_ENP 0x01 /* end of packet */
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#define LE_T1_BITS \
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"\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
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/* Transmit message descriptor 3 (tmd3) */
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#define LE_T3_BUFF 0x8000 /* buffer error */
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#define LE_T3_UFLO 0x4000 /* underflow error */
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#define LE_T3_LCOL 0x1000 /* late collision */
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#define LE_T3_LCAR 0x0800 /* loss of carrier */
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#define LE_T3_RTRY 0x0400 /* retry error */
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#define LE_T3_TDR_MASK 0x03ff /* time domain reflectometry counter */
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#define LE_XMD2_ONES 0xf000
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#define LE_T3_BITS \
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"\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY"
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#define LE_ADDR_LOW_MASK (0xffff)
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