342 lines
7.2 KiB
C
342 lines
7.2 KiB
C
/* $NetBSD: cpufunc.h,v 1.17 2007/05/21 08:10:39 fvdl Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _AMD64_CPUFUNC_H_
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#define _AMD64_CPUFUNC_H_
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/*
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* Functions to provide access to i386-specific instructions.
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*/
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <machine/segments.h>
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#include <machine/specialreg.h>
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#ifdef _KERNEL
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void x86_pause(void);
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#else
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static __inline void
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x86_pause(void)
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{
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__asm volatile("pause");
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}
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#endif
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/*
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* XXX if lfence isn't available...
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*
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* memory clobber to avoid compiler reordering.
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*/
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static __inline void
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x86_lfence(void)
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{
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__asm volatile("lfence" : : : "memory");
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}
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static __inline void
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x86_sfence(void)
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{
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__asm volatile("sfence" : : : "memory");
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}
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static __inline void
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x86_mfence(void)
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{
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__asm volatile("mfence" : : : "memory");
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}
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#ifdef _KERNEL
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void x86_flush(void);
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void x86_patch(void);
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extern int cpu_feature;
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static __inline void
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invlpg(u_int64_t addr)
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{
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__asm volatile("invlpg (%0)" : : "r" (addr) : "memory");
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}
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static __inline void
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lidt(struct region_descriptor *region)
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{
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__asm volatile("lidt %0" : : "m" (*region));
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}
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static __inline void
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lldt(u_short sel)
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{
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__asm volatile("lldt %0" : : "r" (sel));
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}
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static __inline void
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ltr(u_short sel)
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{
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__asm volatile("ltr %0" : : "r" (sel));
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}
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static __inline void
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lcr8(u_int val)
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{
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u_int64_t val64 = val;
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__asm volatile("movq %0,%%cr8" : : "r" (val64));
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}
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/*
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* Upper 32 bits are reserved anyway, so just keep this 32bits.
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*/
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static __inline void
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lcr0(u_int val)
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{
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u_int64_t val64 = val;
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__asm volatile("movq %0,%%cr0" : : "r" (val64));
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}
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static __inline u_int
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rcr0(void)
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{
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u_int64_t val64;
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u_int val;
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__asm volatile("movq %%cr0,%0" : "=r" (val64));
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val = val64;
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return val;
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}
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static __inline u_int64_t
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rcr2(void)
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{
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u_int64_t val;
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__asm volatile("movq %%cr2,%0" : "=r" (val));
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return val;
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}
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static __inline void
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lcr3(u_int64_t val)
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{
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__asm volatile("movq %0,%%cr3" : : "r" (val));
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}
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static __inline u_int64_t
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rcr3(void)
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{
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u_int64_t val;
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__asm volatile("movq %%cr3,%0" : "=r" (val));
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return val;
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}
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/*
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* Same as for cr0. Don't touch upper 32 bits.
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*/
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static __inline void
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lcr4(u_int val)
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{
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u_int64_t val64 = val;
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__asm volatile("movq %0,%%cr4" : : "r" (val64));
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}
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static __inline u_int
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rcr4(void)
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{
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u_int val;
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u_int64_t val64;
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__asm volatile("movq %%cr4,%0" : "=r" (val64));
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val = val64;
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return val;
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}
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static __inline void
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tlbflush(void)
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{
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u_int64_t val;
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__asm volatile("movq %%cr3,%0" : "=r" (val));
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__asm volatile("movq %0,%%cr3" : : "r" (val));
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}
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static __inline void
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tlbflushg(void)
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{
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/*
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* Big hammer: flush all TLB entries, including ones from PTE's
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* with the G bit set. This should only be necessary if TLB
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* shootdown falls far behind.
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*
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* Intel Architecture Software Developer's Manual, Volume 3,
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* System Programming, section 9.10, "Invalidating the
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* Translation Lookaside Buffers (TLBS)":
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* "The following operations invalidate all TLB entries, irrespective
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* of the setting of the G flag:
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* ...
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* "(P6 family processors only): Writing to control register CR4 to
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* modify the PSE, PGE, or PAE flag."
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*
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* (the alternatives not quoted above are not an option here.)
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*
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* If PGE is not in use, we reload CR3 for the benefit of
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* pre-P6-family processors.
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*/
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if (cpu_feature & CPUID_PGE) {
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u_int cr4 = rcr4();
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lcr4(cr4 & ~CR4_PGE);
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lcr4(cr4);
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} else
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tlbflush();
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}
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#ifdef notyet
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void setidt __P((int idx, /*XXX*/void *func, int typ, int dpl));
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#endif
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/* XXXX ought to be in psl.h with spl() functions */
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static __inline void
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disable_intr(void)
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{
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__asm volatile("cli");
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}
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static __inline void
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enable_intr(void)
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{
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__asm volatile("sti");
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}
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static __inline u_long
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read_rflags(void)
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{
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u_long ef;
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__asm volatile("pushfq; popq %0" : "=r" (ef));
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return (ef);
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}
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static __inline void
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write_rflags(u_long ef)
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{
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__asm volatile("pushq %0; popfq" : : "r" (ef));
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}
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static __inline u_int64_t
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rdmsr(u_int msr)
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{
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uint32_t hi, lo;
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__asm volatile("rdmsr" : "=d" (hi), "=a" (lo) : "c" (msr));
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return (((uint64_t)hi << 32) | (uint64_t) lo);
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}
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static __inline void
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wrmsr(u_int msr, u_int64_t newval)
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{
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__asm volatile("wrmsr" :
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: "a" (newval & 0xffffffff), "d" (newval >> 32), "c" (msr));
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}
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/*
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* Some of the undocumented AMD64 MSRs need a 'passcode' to access.
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*
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* See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
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*/
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#define OPTERON_MSR_PASSCODE 0x9c5a203a
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static __inline u_int64_t
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rdmsr_locked(u_int msr, u_int code)
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{
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uint32_t hi, lo;
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__asm volatile("rdmsr"
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: "=d" (hi), "=a" (lo)
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: "c" (msr), "D" (code));
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return (((uint64_t)hi << 32) | (uint64_t) lo);
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}
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static __inline void
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wrmsr_locked(u_int msr, u_int code, u_int64_t newval)
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{
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__asm volatile("wrmsr"
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:
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: "a" (newval & 0xffffffff), "d" (newval >> 32), "c" (msr),
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"D" (code));
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}
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static __inline void
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wbinvd(void)
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{
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__asm volatile("wbinvd");
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}
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static __inline u_int64_t
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rdtsc(void)
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{
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uint32_t hi, lo;
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__asm volatile("rdtsc" : "=d" (hi), "=a" (lo));
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return (((uint64_t)hi << 32) | (uint64_t) lo);
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}
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static __inline u_int64_t
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rdpmc(u_int pmc)
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{
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uint32_t hi, lo;
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__asm volatile("rdpmc" : "=d" (hi), "=a" (lo) : "c" (pmc));
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return (((uint64_t)hi << 32) | (uint64_t) lo);
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}
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/* Break into DDB/KGDB. */
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static __inline void
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breakpoint(void)
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{
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__asm volatile("int $3");
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}
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#define read_psl() read_rflags()
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#define write_psl(x) write_rflags(x)
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#endif /* _KERNEL */
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#endif /* !_AMD64_CPUFUNC_H_ */
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