136 lines
6.2 KiB
C
136 lines
6.2 KiB
C
/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)dmareg.h 8.1 (Berkeley) 6/11/93
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*
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* from: Header: dmareg.h,v 1.6 93/04/27 14:39:17 torek Exp (LBL)
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* $Id: dmareg.h,v 1.1 1993/10/02 10:23:49 deraadt Exp $
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*/
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/*
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* Sun-4c Sbus slot 0 DMA registers.
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*
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* Note that the dma_addr on the rev 1 gate array cannot increment
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* across a 16 MB boundary (the counter is only 24 bits wide; the
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* top 8 bits are simply latched).
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*/
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struct dmareg {
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u_long dma_csr; /* control/status register */
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u_long dma_addr; /* address (virtual: is fed to MMU) */
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u_long dma_bc; /* byte count (not used) */
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u_long dma_diag; /* diagnostic register (not used) */
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};
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/*
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* Bits in dma_csr.
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* DMA chip revision numbers are confusing (rev 3 = `DMA2'?!).
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* Not my fault; we just live with what they give us....
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*
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* Notes in [brackets]:
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* 1: used this way in rev 1 (`DMA') chips.
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* 2: used this way in rev 2 (`DMA+') chips.
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* 3: used this way in rev 3 (`DMA2') chips.
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* R: not self-clearing, must be reset after being set.
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* D: `drain' is like Unibus `bdp purge', i.e., it tells
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* the chip to finish up, because there is no more data
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* going into the buffer register. Supposed to be needed
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* only in rev 1, but apparently needed or harmless in all
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* revs. Self-clearing (hence write-only).
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* I: also enables scsi interrupts.
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*/
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#define DMA_REV(csr) (((csr) >> 28) & 0xf) /* device id field */
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#define DMAREV_1 0x8 /* rev 1 DMA gate array */
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#define DMAREV_2 0x9 /* rev 2 DMA gate array (`DMA+') */
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#define DMAREV_3 0xa /* rev 3 DMA gate array (`DMA2') */
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#define DMA_1ZERO 0x0fff0000 /* unused; reads as zero [1] */
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#define DMA_NAL 0x08000000 /* next address loaded [2] (ro) */
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#define DMA_AL 0x04000000 /* address loaded [2] (ro) */
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#define DMA_ON 0x02000000 /* working [2] (ro) */
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#define DMA_NAE 0x01000000 /* next-address enable [2] (rw) */
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#define DMA_DTCI 0x00800000 /* disable DMA_TC intr [2] (rw) */
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#define DMA_TURBO 0x00400000 /* faster 53C90A mode [2] (rw) */
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#define DMA_LERR 0x00200000 /* LANCE error [2] (ro) */
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#define DMA_TWOCYCLE 0x00200000 /* two cycle mode [3] (rw?) */
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#define DMA_ALE 0x00100000 /* LANCE addr latch ena [2] (rw) */
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#define DMA_2ZERO 0x000f0000 /* unused; reads as zero [2] */
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#define DMA_BURSTMASK 0x000c0000 /* burst mode mask [3] */
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#define DMA_BURST16 0x00000000 /* 16-byte bursts (default) */
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#define DMA_BURST32 0x00040000 /* 32-byte bursts */
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#define DMA_BURST0 0x00080000 /* no bursts */
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#define DMA_ILACC 0x00008000 /* for new AMD ethernet chip [1,2] */
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#define DMA_TC 0x00004000 /* terminal cnt: dma_bc ran out [1,2] */
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#define DMA_BCE 0x00002000 /* byte count enable (leave 0) */
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#define DMA_BO 0x00001800 /* byte offset [1] (ro) */
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#define DMA_RP 0x00000400 /* busy, plz don't flush [1] (ro) */
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#define DMA_ENA 0x00000200 /* enable the dma chip */
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#define DMA_READ 0x00000100 /* set for dev=>mem, i.e., read() */
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#define DMA_RESET 0x00000080 /* reset dma chip [R] */
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#define DMA_DRAIN 0x00000040 /* drain buffered data [D,1] (wo) */
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#define DMA_SLAVEERR 0x00000040 /* slave error [2,3] (ro) */
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#define DMA_FLUSH 0x00000020 /* clear PC, EP, and TC [2,3] (wo) */
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#define DMA_IE 0x00000010 /* interrupt enable [2,3,I] */
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#define DMA_PC 0x0000000c /* bytes in pack reg [1] (ro) */
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#define DMA_DRAINING 0x0000000c /* nonzero => draining [2,3] (ro) */
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#define DMA_EP 0x00000002 /* error pending (ro) */
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#define DMA_IP 0x00000001 /* interrupt pending (ro) */
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#define DMA_REV1_BITS \
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"\20\20ILACC\17TC\16BCE\13RP\12ENA\11READ\10RESET\7DRAIN\2EP\1IP"
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/* Look ma, second system syndrome! */
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#define DMA_REV2_BITS \
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"\20\34NAL\33AL\32ON\31NAE\30DTCI\27TURBO\26LERR\25ALE\
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\20ILACC\17TC\16BCE\12ENA\11READ\10RESET\7SLAVEERR\6FLUSH\5IE\2EP\1IP"
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/* (Note how most of the crap has been discarded now.) */
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#define DMA_REV3_BITS \
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"\20\26TWOCYCLE\16BCE\12ENA\11READ\10RESET\7SLAVEERR\6FLUSH\5IE\2EP\1IP"
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/* DMA_BYTE turns the DMA_BO field into a byte index */
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#define DMA_BYTE(csr) (((csr) >> 11) & 3)
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/* DMA_NPACK turns the DMA_PC field into a byte count */
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#define DMA_NPACK(csr) (((csr) >> 2) & 3)
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/* DMA_INTR is true if the DMA chip says an ESP or DMA interrupt is pending */
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#define DMA_INTR(csr) ((csr) & (DMA_IP | DMA_EP))
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