008816ea4f
Adds (most) support for ARC platform to port-independent mips code. Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by comparison to the OpenBSD 2.1 codebase of Soda's ARC port. Open issues: * Still no support for r4600 or mipsIV CPUs with two-way L1 cache. Code derived from Per Fogelstrom's OpenBSD source doesn't work on mips3 pmaxes with L2 cache. * Still some port-specific #ifdefs, for interrupt enable and pmax L2 cache-size. Needs more thought, but overlaps with work-in-progress by Tohru and Tsubai on spl()s and related stuff. |
||
|---|---|---|
| .. | ||
| alpha | ||
| arm32 | ||
| i386 | ||
| m68k | ||
| mips | ||
| ns32k | ||
| powerpc | ||
| sparc | ||
| sparc64 | ||
| vax | ||