433 lines
10 KiB
C
433 lines
10 KiB
C
/* $NetBSD: isadma.c,v 1.1 1998/06/08 17:49:44 tv Exp $ */
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/*
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* Copyright 1997
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* Digital Equipment Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and conditions.
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* Subject to these conditions, you may download, copy, install,
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* use, modify and distribute this software in source and/or binary
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* form. No title or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions as
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* they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or logo of
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* Digital Equipment Corporation. Neither the "Digital Equipment
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* Corporation" name nor any trademark or logo of Digital Equipment
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* Corporation may be used to endorse or promote products derived
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* from this software without the prior written permission of
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* Digital Equipment Corporation.
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*
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* 3) This software is provided "AS-IS" and any express or implied
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* warranties, including but not limited to, any implied warranties
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* of merchantability, fitness for a particular purpose, or
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* non-infringement are disclaimed. In no event shall DIGITAL be
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* liable for any damages whatsoever, and in particular, DIGITAL
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* shall not be liable for special, indirect, consequential, or
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* incidental damages or damages for lost profits, loss of
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* revenue or loss of use, whether such damages arise in contract,
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* negligence, tort, under statute, in equity, at law or otherwise,
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* even if advised of the possibility of such damage.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/file.h>
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#include <sys/buf.h>
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#include <sys/syslog.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/uio.h>
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#include <vm/vm.h>
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#include <machine/pio.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isadmareg.h>
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#include <arm32/isa/isadmavar.h>
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/* region of physical memory known to be contiguous */
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vm_offset_t isaphysmem;
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static caddr_t dma_bounce[8]; /* XXX */
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static char bounced[8]; /* XXX */
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#define MAXDMASZ 512 /* XXX */
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static u_int8_t dma_finished;
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static u_int8_t dma_buffer_used=0;
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static unsigned isa_dma_masks = 0xFF;
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static int isa_dma_frozen = 0;
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#define ISA_DMA_MASK_SET(CHAN) isa_dma_masks |= (1 << (CHAN))
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#define ISA_DMA_MASK_CLR(CHAN) isa_dma_masks &= ~(1 << (CHAN))
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/* high byte of address is stored in this port for i-th dma channel */
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static int dmapageport[2][4] = {
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{0x87, 0x83, 0x81, 0x82},
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{0x8f, 0x8b, 0x89, 0x8a}
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};
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static u_int8_t dmamode[4] = {
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DMA37MD_READ | DMA37MD_SINGLE,
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DMA37MD_WRITE | DMA37MD_SINGLE,
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DMA37MD_READ | DMA37MD_LOOP,
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DMA37MD_WRITE | DMA37MD_LOOP
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};
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int isa_dmarangecheck __P((vm_offset_t, u_long, int));
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caddr_t isa_allocphysmem __P((caddr_t, unsigned, void (*)(void)));
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void isa_freephysmem __P((caddr_t, unsigned));
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#ifdef SHARK
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/* returns a pointer to the dma buffer if it is available,
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* otherwise will return null.
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*/
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caddr_t isa_dmabuffer_get()
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{
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caddr_t buffer;
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int x;
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x = splhigh();
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if (dma_buffer_used == 0)
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{
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dma_buffer_used = 1;
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buffer = (caddr_t) isaphysmem;
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}
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else
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{
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/* no-can-do, already in use */
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buffer = (caddr_t) NULL;
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}
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splx(x);
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return buffer;
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}
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/* relinquishes the dma buffer, this does no checks
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*/
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void isa_dmabuffer_finish()
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{
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dma_buffer_used = 0;
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}
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#endif
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/*
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* isa_dmacascade(): program 8237 DMA controller channel to accept
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* external dma control by a board.
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*/
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void
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isa_dmacascade(chan)
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int chan;
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{
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#ifdef ISADMA_DEBUG
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if (chan < 0 || chan > 7)
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panic("isa_dmacascade: impossible request");
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#endif
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/* set dma channel mode, and set dma channel mode */
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if ((chan & 4) == 0) {
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outb(IO_DMA1 + DMA1_MODE, chan | DMA37MD_CASCADE);
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ISA_DMA_MASK_CLR(chan);
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if (!isa_dma_frozen)
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outb(IO_DMA1 + DMA1_SMSK, chan);
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} else {
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outb(IO_DMA2 + DMA2_MODE, (chan & 3) | DMA37MD_CASCADE);
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ISA_DMA_MASK_CLR(chan);
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if (!isa_dma_frozen)
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outb(IO_DMA2 + DMA2_SMSK, (chan & 3));
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}
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}
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/*
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* isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
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* problems by using a bounce buffer.
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*/
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void
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isa_dmastart(flags, addr, nbytes, chan)
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int flags;
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caddr_t addr;
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vm_size_t nbytes;
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int chan;
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{
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vm_offset_t phys;
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int waport;
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caddr_t newaddr;
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#ifdef ISADMA_DEBUG
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if (chan < 0 || chan > 7 ||
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((chan & 4) ? (nbytes >= (1<<17) || nbytes & 1 || (u_int)addr & 1) :
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(nbytes >= (1<<16))))
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panic("isa_dmastart: impossible request");
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#endif
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if (isa_dmarangecheck((vm_offset_t) addr, nbytes, chan)) {
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if (dma_bounce[chan] == 0)
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dma_bounce[chan] =
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/*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
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(caddr_t) isaphysmem + NBPG*chan;
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bounced[chan] = 1;
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newaddr = dma_bounce[chan];
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*(int *) newaddr = 0; /* XXX */
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/* copy bounce buffer on write */
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if ((flags & DMAMODE_READ) == 0)
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bcopy(addr, newaddr, nbytes);
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addr = newaddr;
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}
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/* translate to physical */
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phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
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dma_finished &= ~(1 << chan);
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if ((chan & 4) == 0) {
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/*
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* Program one of DMA channels 0..3. These are
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* byte mode channels.
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*/
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/* set dma channel mode, and reset address ff */
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outb(IO_DMA1 + DMA1_MODE, chan | dmamode[flags]);
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outb(IO_DMA1 + DMA1_FFC, 0);
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/* send start address */
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waport = IO_DMA1 + DMA1_CHN(chan);
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outb(dmapageport[0][chan], phys>>16);
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outb(waport, phys);
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outb(waport, phys>>8);
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/* send count */
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outb(waport + 1, --nbytes);
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outb(waport + 1, nbytes>>8);
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/* unmask channel */
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ISA_DMA_MASK_CLR(chan);
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if (!isa_dma_frozen)
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outb(IO_DMA1 + DMA1_SMSK, chan | DMA37SM_CLEAR);
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} else {
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/*
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* Program one of DMA channels 4..7. These are
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* word mode channels.
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*/
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/* set dma channel mode, and reset address ff */
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outb(IO_DMA2 + DMA2_MODE, (chan & 3) | dmamode[flags]);
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outb(IO_DMA2 + DMA2_FFC, 0);
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/* send start address */
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waport = IO_DMA2 + DMA2_CHN(chan & 3);
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outb(dmapageport[1][chan & 3], phys>>16);
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phys >>= 1;
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outb(waport, phys);
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outb(waport, phys>>8);
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/* send count */
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nbytes >>= 1;
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outb(waport + 2, --nbytes);
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outb(waport + 2, nbytes>>8);
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/* unmask channel */
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ISA_DMA_MASK_CLR(chan);
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if (!isa_dma_frozen)
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outb(IO_DMA2 + DMA2_SMSK, (chan & 3) | DMA37SM_CLEAR);
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}
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}
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void
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isa_dmaabort(chan)
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int chan;
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{
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#ifdef ISADMA_DEBUG
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if (chan < 0 || chan > 7)
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panic("isa_dmaabort: impossible request");
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#endif
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bounced[chan] = 0;
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/* mask channel */
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ISA_DMA_MASK_SET(chan);
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if ((chan & 4) == 0)
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if (!isa_dma_frozen)
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outb(IO_DMA1 + DMA1_SMSK, DMA37SM_SET | chan);
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else
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if (!isa_dma_frozen)
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outb(IO_DMA2 + DMA2_SMSK, DMA37SM_SET | (chan & 3));
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}
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int
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isa_dmafinished(chan)
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int chan;
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{
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#ifdef ISADMA_DEBUG
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if (chan < 0 || chan > 7)
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panic("isa_dmafinished: impossible request");
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#endif
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/* check that the terminal count was reached */
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if ((chan & 4) == 0)
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dma_finished |= inb(IO_DMA1 + DMA1_SR) & 0x0f;
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else
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dma_finished |= (inb(IO_DMA2 + DMA2_SR) & 0x0f) << 4;
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return ((dma_finished & (1 << chan)) != 0);
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}
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void
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isa_dmadone(flags, addr, nbytes, chan)
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int flags;
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caddr_t addr;
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vm_size_t nbytes;
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int chan;
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{
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#ifdef ISADMA_DEBUG
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if (chan < 0 || chan > 7)
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panic("isa_dmadone: impossible request");
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#endif
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if (!isa_dmafinished(chan))
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printf("isa_dmadone: channel %d not finished\n", chan);
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/* mask channel */
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ISA_DMA_MASK_SET(chan);
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if ((chan & 4) == 0)
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if (!isa_dma_frozen)
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outb(IO_DMA1 + DMA1_SMSK, DMA37SM_SET | chan);
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else
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if (!isa_dma_frozen)
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outb(IO_DMA2 + DMA2_SMSK, DMA37SM_SET | (chan & 3));
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/* copy bounce buffer on read */
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if (bounced[chan]) {
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bcopy(dma_bounce[chan], addr, nbytes);
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bounced[chan] = 0;
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}
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}
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/*
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* Check for problems with the address range of a DMA transfer
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* (non-contiguous physical pages, outside of bus address space,
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* crossing DMA page boundaries).
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* Return true if special handling needed.
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*/
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int
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isa_dmarangecheck(va, length, chan)
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vm_offset_t va;
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u_long length;
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int chan;
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{
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vm_offset_t phys, priorpage = 0, endva;
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u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
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endva = round_page(va + length);
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for (; va < endva ; va += NBPG) {
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phys = trunc_page(pmap_extract(pmap_kernel(), va));
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if (phys == 0)
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panic("isa_dmacheck: no physical page present");
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#ifdef ISA_MACHDEP_DMARANGECHECK
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if (isa_machdep_dmarangecheck(phys, NBPG))
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#else
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if (phys >= (1<<24))
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#endif
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return 1;
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if (priorpage) {
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if (priorpage + NBPG != phys)
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return 1;
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/* check if crossing a DMA page boundary */
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if ((priorpage ^ phys) & dma_pgmsk)
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return 1;
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}
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priorpage = phys;
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}
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return 0;
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}
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/* head of queue waiting for physmem to become available */
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struct buf isa_physmemq;
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/* blocked waiting for resource to become free for exclusive use */
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static int isaphysmemflag;
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/* if waited for and call requested when free (B_CALL) */
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static void (*isaphysmemunblock) __P((void)); /* needs to be a list */
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/*
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* Allocate contiguous physical memory for transfer, returning
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* a *virtual* address to region. May block waiting for resource.
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* (assumed to be called at splbio())
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*/
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caddr_t
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isa_allocphysmem(ca, length, func)
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caddr_t ca;
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unsigned length;
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void (*func) __P((void));
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{
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isaphysmemunblock = func;
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while (isaphysmemflag & B_BUSY) {
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isaphysmemflag |= B_WANTED;
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sleep((caddr_t)&isaphysmemflag, PRIBIO);
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}
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isaphysmemflag |= B_BUSY;
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return((caddr_t)isaphysmem);
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}
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/*
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* Free contiguous physical memory used for transfer.
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* (assumed to be called at splbio())
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*/
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void
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isa_freephysmem(va, length)
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caddr_t va;
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unsigned length;
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{
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isaphysmemflag &= ~B_BUSY;
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if (isaphysmemflag & B_WANTED) {
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isaphysmemflag &= B_WANTED;
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wakeup((caddr_t)&isaphysmemflag);
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if (isaphysmemunblock)
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(*isaphysmemunblock)();
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}
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}
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void
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isa_dmafreeze()
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{
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int x;
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x = splhigh();
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if (!isa_dma_frozen) {
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outb(IO_DMA1 + DMA1_MASK, 0xF);
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outb(IO_DMA2 + DMA2_MASK, 0xF);
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/* blam! */
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}
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isa_dma_frozen++;
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splx(x);
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}
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void
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isa_dmathaw()
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{
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int x;
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x = splhigh();
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isa_dma_frozen--;
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if (isa_dma_frozen == 0) {
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outb(IO_DMA1 + DMA1_MASK, isa_dma_masks & 0xF);
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outb(IO_DMA2 + DMA2_MASK, (isa_dma_masks >> 4) & 0xF);
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} else if (isa_dma_frozen < 0) {
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isa_dma_frozen = 0;
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}
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splx(x);
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}
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