048e948791
I added two new bitfields to ncr_softc. They flag which devices have been selected, and which ones have failed to go to message out when selected with ATN. If a target fails to go to message out the first time it is selected, it goes into the latter bitfield. If it fails thereafter, we treat it as we did before.
259 lines
9.1 KiB
C
259 lines
9.1 KiB
C
/* $NetBSD: ncr5380reg.h,v 1.3 1995/09/15 01:52:20 briggs Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Leo Weppelman.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NCR5380REG_H
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#define _NCR5380REG_H
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/*
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* NCR5380 common interface definitions.
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*/
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/*
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* Register numbers: (first argument to GET/SET_5380_REG )
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*/
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#define NCR5380_DATA 0 /* Data register */
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#define NCR5380_ICOM 1 /* Initiator command register */
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#define NCR5380_MODE 2 /* Mode register */
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#define NCR5380_TCOM 3 /* Target command register */
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#define NCR5380_IDSTAT 4 /* Bus status register */
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#define NCR5380_DMSTAT 5 /* DMA status register */
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#define NCR5380_TRCV 6 /* Target receive register */
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#define NCR5380_IRCV 7 /* Initiator receive register */
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/*
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* Definitions for Initiator command register.
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*/
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#define SC_A_RST 0x80 /* RW - Assert RST */
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#define SC_TEST 0x40 /* W - Test mode */
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#define SC_AIP 0x40 /* R - Arbitration in progress */
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#define SC_LA 0x20 /* R - Lost arbitration */
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#define SC_A_ACK 0x10 /* RW - Assert ACK */
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#define SC_A_BSY 0x08 /* RW - Assert BSY */
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#define SC_A_SEL 0x04 /* RW - Assert SEL */
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#define SC_A_ATN 0x02 /* RW - Assert ATN */
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#define SC_ADTB 0x01 /* RW - Assert Data To Bus */
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/*
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* Definitions for mode register
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*/
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#define SC_B_DMA 0x80 /* RW - Block mode DMA (not on TT!) */
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#define SC_T_MODE 0x40 /* RW - Target mode */
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#define SC_E_PAR 0x20 /* RW - Enable parity check */
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#define SC_E_PARI 0x10 /* RW - Enable parity interrupt */
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#define SC_E_EOPI 0x08 /* RW - Enable End Of Process Interrupt */
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#define SC_MON_BSY 0x04 /* RW - Monitor BSY */
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#define SC_M_DMA 0x02 /* RW - Set DMA mode */
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#define SC_ARBIT 0x01 /* RW - Arbitrate */
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/*
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* Definitions for tcom register
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*/
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#define SC_LBS 0x80 /* RW - Last Byte Send (not on TT!) */
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#define SC_A_REQ 0x08 /* RW - Assert REQ */
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#define SC_A_MSG 0x04 /* RW - Assert MSG */
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#define SC_A_CD 0x02 /* RW - Assert C/D */
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#define SC_A_IO 0x01 /* RW - Assert I/O */
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/*
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* Definitions for idstat register
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*/
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#define SC_S_RST 0x80 /* R - RST is set */
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#define SC_S_BSY 0x40 /* R - BSY is set */
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#define SC_S_REQ 0x20 /* R - REQ is set */
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#define SC_S_MSG 0x10 /* R - MSG is set */
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#define SC_S_CD 0x08 /* R - C/D is set */
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#define SC_S_IO 0x04 /* R - I/O is set */
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#define SC_S_SEL 0x02 /* R - SEL is set */
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#define SC_S_PAR 0x01 /* R - Parity bit */
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/*
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* Definitions for dmastat register
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*/
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#define SC_END_DMA 0x80 /* R - End of DMA */
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#define SC_DMA_REQ 0x40 /* R - DMA request */
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#define SC_PAR_ERR 0x20 /* R - Parity error */
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#define SC_IRQ_SET 0x10 /* R - IRQ is active */
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#define SC_PHS_MTCH 0x08 /* R - Phase Match */
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#define SC_BSY_ERR 0x04 /* R - Busy error */
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#define SC_ATN_STAT 0x02 /* R - State of ATN line */
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#define SC_ACK_STAT 0x01 /* R - State of ACK line */
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#define SC_S_SEND 0x00 /* W - Start DMA output */
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#define SC_CLINT { /* Clear interrupts */ \
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int i = GET_5380_REG(NCR5380_IRCV); \
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}
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/*
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* Definition of SCSI-bus phases. The values are determined by signals
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* on the SCSI-bus. DO NOT CHANGE!
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* The values must be used to index the pointers in SCSI-PARMS.
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*/
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#define NR_PHASE 8
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#define PH_DATAOUT 0
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#define PH_DATAIN 1
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#define PH_CMD 2
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#define PH_STATUS 3
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#define PH_RES1 4
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#define PH_RES2 5
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#define PH_MSGOUT 6
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#define PH_MSGIN 7
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#define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
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#define PH_IN(phase) (phase & 1) /* TRUE if input phase */
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/*
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* Id of Host-adapter
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*/
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#define SC_HOST_ID 0x80
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/*
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* Base setting for 5380 mode register
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*/
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#define IMODE_BASE SC_E_PAR
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/*
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* SCSI completion status codes, should move to sys/scsi/????
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*/
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#define SCSMASK 0x1e /* status code mask */
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#define SCSGOOD 0x00 /* good status */
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#define SCSCHKC 0x02 /* check condition */
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#define SCSBUSY 0x08 /* busy status */
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#define SCSCMET 0x04 /* condition met / good */
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/*
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* Return values of check_intr()
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*/
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#define INTR_SPURIOUS 0
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#define INTR_RESEL 2
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#define INTR_DMA 3
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struct ncr_softc {
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struct device sc_dev;
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struct scsi_link sc_link;
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/*
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* Some (pre-SCSI2) devices don't support select with ATN.
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* If the device responds to select with ATN by going into
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* command phase (ignoring ATN), then we flag it in the
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* following bitmask.
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* We also keep track of which devices have been selected
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* before. This allows us to not even try raising ATN if
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* the target doesn't respond to it the first time.
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*/
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u_int8_t sc_noselatn;
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u_int8_t sc_selected;
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};
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/*
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* Max. number of dma-chains per request
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*/
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#define MAXDMAIO (MAXPHYS/NBPG + 1)
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/*
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* Some requests are not contiguous in physical memory. We need to break them
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* up into contiguous parts for DMA.
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*/
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struct dma_chain {
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u_int dm_count;
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u_long dm_addr;
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};
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/*
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* Define our issue, free and disconnect queue's.
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*/
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typedef struct req_q {
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struct req_q *next; /* next in free, issue or discon queue */
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struct req_q *link; /* next linked command to execute */
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struct scsi_xfer *xs; /* request from high-level driver */
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u_short dr_flag; /* driver state */
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u_char phase; /* current SCSI phase */
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u_char msgout; /* message to send when requested */
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u_char targ_id; /* target for command */
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u_char targ_lun; /* lun for command */
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u_char status; /* returned status byte */
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u_char message; /* returned message byte */
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u_char *bounceb; /* allocated bounce buffer */
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u_char *bouncerp; /* bounce read-pointer */
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struct dma_chain dm_chain[MAXDMAIO];
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struct dma_chain *dm_cur; /* current dma-request */
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struct dma_chain *dm_last; /* last dma-request */
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long xdata_len; /* length of transfer */
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u_char *xdata_ptr; /* virtual address of transfer */
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struct scsi_generic xcmd; /* command to execute */
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} SC_REQ;
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/*
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* Values for dr_flag:
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*/
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#define DRIVER_IN_DMA 0x01 /* Non-polled DMA activated */
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#define DRIVER_AUTOSEN 0x02 /* Doing automatic sense */
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#define DRIVER_NOINT 0x04 /* We are booting: no interrupts */
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#define DRIVER_DMAOK 0x08 /* DMA can be used on this request */
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#define DRIVER_BOUNCING 0x10 /* Using the bounce buffer */
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/* XXX: Should go to ncr5380var.h */
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static SC_REQ *issue_q = NULL; /* Commands waiting to be issued*/
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static SC_REQ *discon_q = NULL; /* Commands disconnected */
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static SC_REQ *connected = NULL; /* Command currently connected */
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/*
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* Function decls:
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*/
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static int transfer_pio __P((u_char *, u_char *, u_long *, int));
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static int wait_req_true __P((void));
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static int wait_req_false __P((void));
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static int scsi_select __P((SC_REQ *, int));
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static int handle_message __P((SC_REQ *, u_int));
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static void ack_message __P((void));
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static void nack_message __P((SC_REQ *));
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static int information_transfer __P((void));
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static void reselect __P((struct ncr_softc *));
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static int dma_ready __P((void));
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static void transfer_dma __P((SC_REQ *, u_int, int));
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static int check_autosense __P((SC_REQ *, int));
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static int reach_msg_out __P((struct ncr_softc *, u_long));
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static int check_intr __P((struct ncr_softc *));
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static void scsi_reset __P((struct ncr_softc *));
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static int scsi_dmaok __P((SC_REQ *));
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static void run_main __P((struct ncr_softc *));
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static void scsi_main __P((struct ncr_softc *));
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static void ncr_ctrl_intr __P((struct ncr_softc *));
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static void ncr_dma_intr __P((struct ncr_softc *));
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static void ncr_tprint __P((SC_REQ *, char *, ...));
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static void ncr_aprint __P((struct ncr_softc *, char *, ...));
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static void show_request __P((SC_REQ *, char *));
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static void show_phase __P((SC_REQ *, int));
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static void show_signals __P((u_char, u_char));
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#endif /* _NCR5380REG_H */
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