612 lines
16 KiB
C
612 lines
16 KiB
C
/* $NetBSD: lsi64854.c,v 1.5 1999/03/23 00:32:27 pk Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/ic/lsi64854reg.h>
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#include <dev/ic/lsi64854var.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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void lsi64854_reset __P((struct lsi64854_softc *));
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int lsi64854_setup __P((struct lsi64854_softc *, caddr_t *, size_t *,
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int, size_t *));
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int lsi64854_setup_pp __P((struct lsi64854_softc *, caddr_t *, size_t *,
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int, size_t *));
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#ifdef DEBUG
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int lsi64854debug = 0;
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#define DPRINTF(x) do { if (lsi64854debug != 0) printf x ; } while (0)
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#else
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#define DPRINTF(x)
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#endif
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#define MAX_DMA_SZ (16*1024*1024)
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/*
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* Finish attaching this DMA device.
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* Front-end must fill in these fields:
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* sc_bustag
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* sc_dmatag
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* sc_regs
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* sc_burst
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* sc_channel (one of SCSI, ENET, PP)
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* sc_client (one of SCSI, ENET, PP `soft_c' pointers)
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*/
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void
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lsi64854_attach(sc)
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struct lsi64854_softc *sc;
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{
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/* Indirect functions */
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switch (sc->sc_channel) {
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case L64854_CHANNEL_SCSI:
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sc->intr = lsi64854_scsi_intr;
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sc->setup = lsi64854_setup;
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break;
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case L64854_CHANNEL_ENET:
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sc->intr = lsi64854_enet_intr;
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break;
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case L64854_CHANNEL_PP:
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sc->setup = lsi64854_setup_pp;
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break;
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default:
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printf("%s: unknown channel\n", sc->sc_dev.dv_xname);
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}
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sc->reset = lsi64854_reset;
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/* Allocate a dmamap */
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if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ,
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0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) {
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printf("%s: dma map create failed\n", sc->sc_dev.dv_xname);
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return;
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}
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printf(": rev ");
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sc->sc_rev = L64854_GCSR(sc) & L64854_DEVID;
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switch (sc->sc_rev) {
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case DMAREV_0:
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printf("0");
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break;
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case DMAREV_ESC:
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printf("esc");
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break;
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case DMAREV_1:
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printf("1");
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break;
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case DMAREV_PLUS:
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printf("1+");
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break;
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case DMAREV_2:
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printf("2");
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break;
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default:
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printf("unknown (0x%x)", sc->sc_rev);
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}
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printf("\n");
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}
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#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
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int count = 500000; \
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while ((COND) && --count > 0) DELAY(1); \
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if (count == 0) { \
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printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
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(u_long)L64854_GCSR(SC)); \
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if (DONTPANIC) \
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printf(MSG); \
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else \
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panic(MSG); \
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} \
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} while (0)
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#define DMA_DRAIN(sc, dontpanic) do { \
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u_int32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_ESC_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
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/* \
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* Select drain bit based on revision \
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* also clears errors and D_TC flag \
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*/ \
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csr = L64854_GCSR(sc); \
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if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
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csr |= D_ESC_DRAIN; \
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else \
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csr |= L64854_INVALIDATE; \
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\
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L64854_SCSR(sc,csr); \
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/* \
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* Wait for draining to finish \
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* rev0 & rev1 call this PACKCNT \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
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} while(0)
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#define DMA_FLUSH(sc, dontpanic) do { \
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u_int32_t csr; \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_ESC_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
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csr = L64854_GCSR(sc); \
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csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
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csr |= L64854_INVALIDATE; \
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L64854_SCSR(sc,csr); \
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} while(0)
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void
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lsi64854_reset(sc)
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struct lsi64854_softc *sc;
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{
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u_int32_t csr;
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DMA_FLUSH(sc, 1);
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csr = L64854_GCSR(sc);
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csr |= L64854_RESET; /* reset DMA */
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L64854_SCSR(sc, csr);
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DELAY(200); /* > 10 Sbus clocks(?) */
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/*DMAWAIT1(sc); why was this here? */
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csr = L64854_GCSR(sc);
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csr &= ~L64854_RESET; /* de-assert reset line */
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L64854_SCSR(sc, csr);
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DELAY(5); /* allow a few ticks to settle */
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csr = L64854_GCSR(sc);
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csr |= L64854_INT_EN; /* enable interrupts */
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if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI)
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csr |= D_FASTER;
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/* Set burst */
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switch (sc->sc_rev) {
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case DMAREV_2:
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csr &= ~L64854_BURST_SIZE;
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if (sc->sc_burst == 32) {
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csr |= L64854_BURST_32;
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} else if (sc->sc_burst == 16) {
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csr |= L64854_BURST_16;
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} else {
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csr |= L64854_BURST_0;
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}
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break;
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case DMAREV_ESC:
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csr |= D_ESC_AUTODRAIN; /* Auto-drain */
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if (sc->sc_burst == 32) {
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csr &= ~D_ESC_BURST;
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} else
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csr |= D_ESC_BURST;
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break;
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default:
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}
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L64854_SCSR(sc, csr);
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sc->sc_active = 0;
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}
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#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1)))
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/*
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* setup a dma transfer
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*/
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int
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lsi64854_setup(sc, addr, len, datain, dmasize)
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struct lsi64854_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize; /* IN-OUT */
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{
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u_int32_t csr;
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DMA_FLUSH(sc, 0);
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#if 0
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DMACSR(sc) &= ~D_INT_EN;
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#endif
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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DPRINTF(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
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*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
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/*
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* the rules say we cannot transfer more than the limit
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* of this DMA chip (64k for old and 16Mb for new),
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* and we cannot cross a 16Mb boundary.
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*/
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*dmasize = sc->sc_dmasize =
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min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
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DPRINTF(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
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/* Program the DMA address */
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if (sc->sc_dmasize) {
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int s = splbio();
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sc->sc_dvmaaddr = *sc->sc_dmaaddr;
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if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
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*sc->sc_dmaaddr, sc->sc_dmasize,
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NULL /* kernel address */,
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BUS_DMA_NOWAIT))
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panic("%s: cannot allocate DVMA address",
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sc->sc_dev.dv_xname);
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splx(s);
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bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap,
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(bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize,
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datain
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? BUS_DMASYNC_PREREAD
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: BUS_DMASYNC_PREWRITE);
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bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR,
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sc->sc_dmamap->dm_segs[0].ds_addr);
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}
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if (sc->sc_rev == DMAREV_ESC) {
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/* DMA ESC chip bug work-around */
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long bcnt = sc->sc_dmasize;
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long eaddr = bcnt + (long)*sc->sc_dmaaddr;
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if ((eaddr & PGOFSET) != 0)
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bcnt = roundup(bcnt, NBPG);
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bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT,
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bcnt);
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}
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/* Setup DMA control register */
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csr = L64854_GCSR(sc);
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if (datain)
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csr |= L64854_WRITE;
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else
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csr &= ~L64854_WRITE;
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csr |= L64854_INT_EN;
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L64854_SCSR(sc, csr);
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return (0);
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}
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/*
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* Pseudo (chained) interrupt from the esp driver to kick the
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* current running DMA transfer. Called from ncr53c9x_intr()
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* for now.
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*
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* return 1 if it was a DMA continue.
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*/
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int
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lsi64854_scsi_intr(arg)
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void *arg;
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{
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struct lsi64854_softc *sc = arg;
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struct ncr53c9x_softc *nsc = sc->sc_client;
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char bits[64];
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int trans, resid;
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u_int32_t csr;
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csr = L64854_GCSR(sc);
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DPRINTF(("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname,
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bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
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bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits))));
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if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
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csr &= ~D_EN_DMA; /* Stop DMA */
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/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
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csr |= D_INVALIDATE|D_SLAVE_ERR;
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L64854_SCSR(sc, csr);
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printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
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bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits)));
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return (-1);
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}
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/* This is an "assertion" :) */
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if (sc->sc_active == 0)
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panic("dmaintr: DMA wasn't active");
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DMA_DRAIN(sc, 0);
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/* DMA has stopped */
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csr &= ~D_EN_DMA;
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L64854_SCSR(sc, csr);
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sc->sc_active = 0;
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if (sc->sc_dmasize == 0) {
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/* A "Transfer Pad" operation completed */
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DPRINTF(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
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NCR_READ_REG(nsc, NCR_TCL) |
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(NCR_READ_REG(nsc, NCR_TCM) << 8),
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NCR_READ_REG(nsc, NCR_TCL),
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NCR_READ_REG(nsc, NCR_TCM)));
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return 0;
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}
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resid = 0;
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/*
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* If a transfer onto the SCSI bus gets interrupted by the device
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* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
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* as residual since the NCR53C9X counter registers get decremented
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* as bytes are clocked into the FIFO.
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*/
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if (!(csr & D_WRITE) &&
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(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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DPRINTF(("dmaintr: empty esp FIFO of %d ", resid));
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}
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if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
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/*
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* `Terminal count' is off, so read the residue
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* out of the NCR53C9X counter registers.
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*/
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resid += (NCR_READ_REG(nsc, NCR_TCL) |
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(NCR_READ_REG(nsc, NCR_TCM) << 8) |
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((nsc->sc_cfg2 & NCRCFG2_FE)
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? (NCR_READ_REG(nsc, NCR_TCH) << 16)
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: 0));
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if (resid == 0 && sc->sc_dmasize == 65536 &&
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(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
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/* A transfer of 64K is encoded as `TCL=TCM=0' */
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resid = 65536;
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}
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trans = sc->sc_dmasize - resid;
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if (trans < 0) { /* transferred < 0 ? */
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#if 0
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/*
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* This situation can happen in perfectly normal operation
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* if the ESP is reselected while using DMA to select
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* another target. As such, don't print the warning.
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*/
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printf("%s: xfer (%d) > req (%d)\n",
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sc->sc_dev.dv_xname, trans, sc->sc_dmasize);
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#endif
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trans = sc->sc_dmasize;
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}
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DPRINTF(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
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NCR_READ_REG(nsc, NCR_TCL),
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NCR_READ_REG(nsc, NCR_TCM),
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(nsc->sc_cfg2 & NCRCFG2_FE)
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? NCR_READ_REG(nsc, NCR_TCH) : 0,
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trans, resid));
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if (sc->sc_dmamap->dm_nsegs > 0) {
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bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap,
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(bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize,
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(csr & D_WRITE) != 0
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? BUS_DMASYNC_POSTREAD
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: BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
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}
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*sc->sc_dmalen -= trans;
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*sc->sc_dmaaddr += trans;
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#if 0 /* this is not normal operation just yet */
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if (*sc->sc_dmalen == 0 ||
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nsc->sc_phase != nsc->sc_prevphase)
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return 0;
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/* and again */
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dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
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return 1;
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#endif
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return 0;
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}
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/*
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* Pseudo (chained) interrupt to le driver to handle DMA errors.
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*/
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int
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lsi64854_enet_intr(arg)
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void *arg;
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{
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struct lsi64854_softc *sc = arg;
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char bits[64];
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u_int32_t csr;
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static int dodrain=0;
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csr = L64854_GCSR(sc);
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if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
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csr &= ~L64854_EN_DMA; /* Stop DMA */
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/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
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csr |= E_INVALIDATE|E_SLAVE_ERR;
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L64854_SCSR(sc, csr);
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printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
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bitmask_snprintf(csr, EDMACSR_BITS, bits,sizeof(bits)));
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DMA_RESET(sc);
|
|
dodrain = 1;
|
|
}
|
|
|
|
if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */
|
|
int i = 10;
|
|
csr |= E_DRAIN;
|
|
L64854_SCSR(sc, csr);
|
|
while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
|
|
delay(1);
|
|
}
|
|
|
|
return (*sc->sc_intrchain)(sc->sc_intrchainarg);
|
|
}
|
|
|
|
/*
|
|
* setup a dma transfer
|
|
*/
|
|
int
|
|
lsi64854_setup_pp(sc, addr, len, datain, dmasize)
|
|
struct lsi64854_softc *sc;
|
|
caddr_t *addr;
|
|
size_t *len;
|
|
int datain;
|
|
size_t *dmasize; /* IN-OUT */
|
|
{
|
|
u_int32_t csr;
|
|
|
|
DMA_FLUSH(sc, 0);
|
|
|
|
sc->sc_dmaaddr = addr;
|
|
sc->sc_dmalen = len;
|
|
|
|
DPRINTF(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
|
|
*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
|
|
|
|
/*
|
|
* the rules say we cannot transfer more than the limit
|
|
* of this DMA chip (64k for old and 16Mb for new),
|
|
* and we cannot cross a 16Mb boundary.
|
|
*/
|
|
*dmasize = sc->sc_dmasize =
|
|
min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
|
|
|
|
DPRINTF(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
|
|
|
|
/* Program the DMA address */
|
|
if (sc->sc_dmasize) {
|
|
int s = splserial(); /* XXX - what shall we choose? */
|
|
sc->sc_dvmaaddr = *sc->sc_dmaaddr;
|
|
if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
|
|
*sc->sc_dmaaddr, sc->sc_dmasize,
|
|
NULL /* kernel address */,
|
|
BUS_DMA_NOWAIT))
|
|
panic("%s: cannot allocate DVMA address",
|
|
sc->sc_dev.dv_xname);
|
|
splx(s);
|
|
bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap,
|
|
(bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize,
|
|
datain
|
|
? BUS_DMASYNC_PREREAD
|
|
: BUS_DMASYNC_PREWRITE);
|
|
bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR,
|
|
sc->sc_dmamap->dm_segs[0].ds_addr);
|
|
|
|
bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT,
|
|
sc->sc_dmasize);
|
|
}
|
|
|
|
/* Setup DMA control register */
|
|
csr = L64854_GCSR(sc);
|
|
#if 0
|
|
/* This bit is read-only in PP csr register */
|
|
if (datain)
|
|
csr |= L64854_WRITE;
|
|
else
|
|
csr &= ~L64854_WRITE;
|
|
#endif
|
|
csr |= L64854_INT_EN;
|
|
L64854_SCSR(sc, csr);
|
|
|
|
return (0);
|
|
}
|
|
/*
|
|
* Parallel port DMA interrupt.
|
|
*/
|
|
int
|
|
lsi64854_pp_intr(arg)
|
|
void *arg;
|
|
{
|
|
struct lsi64854_softc *sc = arg;
|
|
char bits[64];
|
|
int ret, trans, resid = 0;
|
|
u_int32_t csr;
|
|
|
|
csr = L64854_GCSR(sc);
|
|
|
|
DPRINTF(("%s: intr: addr 0x%x, csr %s\n", sc->sc_dev.dv_xname,
|
|
bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
|
|
bitmask_snprintf(csr, PDMACSR_BITS, bits, sizeof(bits))));
|
|
|
|
if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
|
|
csr &= ~P_EN_DMA; /* Stop DMA */
|
|
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
|
|
csr |= P_INVALIDATE|P_SLAVE_ERR;
|
|
L64854_SCSR(sc, csr);
|
|
printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
|
|
bitmask_snprintf(csr, PDMACSR_BITS, bits,sizeof(bits)));
|
|
}
|
|
|
|
ret = (csr & P_INT_PEND) != 0;
|
|
|
|
if (sc->sc_active != 0) {
|
|
DMA_DRAIN(sc, 0);
|
|
resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs,
|
|
L64854_REG_CNT);
|
|
}
|
|
|
|
/* DMA has stopped */
|
|
csr &= ~D_EN_DMA;
|
|
L64854_SCSR(sc, csr);
|
|
sc->sc_active = 0;
|
|
|
|
trans = sc->sc_dmasize - resid;
|
|
if (trans < 0) { /* transferred < 0 ? */
|
|
trans = sc->sc_dmasize;
|
|
}
|
|
*sc->sc_dmalen -= trans;
|
|
*sc->sc_dmaaddr += trans;
|
|
|
|
if (sc->sc_dmamap->dm_nsegs > 0) {
|
|
bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap,
|
|
(bus_addr_t)sc->sc_dvmaaddr, sc->sc_dmasize,
|
|
(csr & D_WRITE) != 0
|
|
? BUS_DMASYNC_POSTREAD
|
|
: BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
|
|
}
|
|
|
|
ret |= (*sc->sc_intrchain)(sc->sc_intrchainarg);
|
|
return (ret != 0);
|
|
}
|