379 lines
8.9 KiB
C
379 lines
8.9 KiB
C
/* $NetBSD: pci_swiz_bus_mem_chipdep.c,v 1.9 1996/10/13 03:00:17 christos Exp $ */
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Common PCI Chipset "bus I/O" functions, for chipsets which have to
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* deal with only a single PCI interface chip in a machine.
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*
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* uses:
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* CHIP name of the 'chip' it's being compiled for.
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* CHIP_D_MEM_BASE Dense Mem space base to use.
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* CHIP_S_MEM_BASE Sparse Mem space base to use.
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*/
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#define __C(A,B) __CONCAT(A,B)
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#define __S(S) __STRING(S)
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int __C(CHIP,_mem_map) __P((void *, bus_mem_addr_t, bus_mem_size_t,
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int, bus_mem_handle_t *));
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void __C(CHIP,_mem_unmap) __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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int __C(CHIP,_mem_subregion) __P((void *, bus_mem_handle_t,
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bus_mem_size_t, bus_mem_size_t, bus_mem_handle_t *));
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u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_mem_handle_t,
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bus_mem_size_t));
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void __C(CHIP,_mem_write_1) __P((void *, bus_mem_handle_t,
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bus_mem_size_t, u_int8_t));
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void __C(CHIP,_mem_write_2) __P((void *, bus_mem_handle_t,
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bus_mem_size_t, u_int16_t));
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void __C(CHIP,_mem_write_4) __P((void *, bus_mem_handle_t,
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bus_mem_size_t, u_int32_t));
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void __C(CHIP,_mem_write_8) __P((void *, bus_mem_handle_t,
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bus_mem_size_t, u_int64_t));
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/* XXX DOES NOT BELONG */
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vm_offset_t __C(CHIP,_XXX_dmamap) __P((void *));
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void
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__C(CHIP,_bus_mem_init)(bc, memv)
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bus_chipset_tag_t bc;
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void *memv;
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{
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bc->bc_m_v = memv;
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bc->bc_m_map = __C(CHIP,_mem_map);
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bc->bc_m_unmap = __C(CHIP,_mem_unmap);
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bc->bc_m_subregion = __C(CHIP,_mem_subregion);
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bc->bc_mr1 = __C(CHIP,_mem_read_1);
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bc->bc_mr2 = __C(CHIP,_mem_read_2);
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bc->bc_mr4 = __C(CHIP,_mem_read_4);
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bc->bc_mr8 = __C(CHIP,_mem_read_8);
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bc->bc_mw1 = __C(CHIP,_mem_write_1);
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bc->bc_mw2 = __C(CHIP,_mem_write_2);
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bc->bc_mw4 = __C(CHIP,_mem_write_4);
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bc->bc_mw8 = __C(CHIP,_mem_write_8);
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/* XXX DOES NOT BELONG */
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bc->bc_XXX_dmamap = __C(CHIP,_XXX_dmamap);
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}
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int
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__C(CHIP,_mem_map)(v, memaddr, memsize, cacheable, memhp)
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void *v;
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bus_mem_addr_t memaddr;
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bus_mem_size_t memsize;
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int cacheable;
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bus_mem_handle_t *memhp;
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{
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if (cacheable) {
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#ifdef CHIP_D_MEM_W1_START
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if (memaddr >= CHIP_D_MEM_W1_START(v) &&
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memaddr <= CHIP_D_MEM_W1_END(v)) {
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*memhp = ALPHA_PHYS_TO_K0SEG(CHIP_D_MEM_W1_BASE(v)) +
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(memaddr & CHIP_D_MEM_W1_MASK(v));
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} else
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#endif
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{
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printf("\n");
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#ifdef CHIP_D_MEM_W1_START
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printf("%s: window[1]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_mem_map)), CHIP_D_MEM_W1_START(v),
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CHIP_D_MEM_W1_END(v)-1);
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#endif
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panic("%s: don't know how to map %lx cacheable\n",
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__S(__C(CHIP,_mem_map)), memaddr);
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}
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} else {
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#ifdef CHIP_S_MEM_W1_START
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if (memaddr >= CHIP_S_MEM_W1_START(v) &&
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memaddr <= CHIP_S_MEM_W1_END(v)) {
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*memhp = (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W1_BASE(v)) >> 5) +
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(memaddr & CHIP_S_MEM_W1_MASK(v));
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} else
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#endif
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#ifdef CHIP_S_MEM_W2_START
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if (memaddr >= CHIP_S_MEM_W2_START(v) &&
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memaddr <= CHIP_S_MEM_W2_END(v)) {
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*memhp = (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W2_BASE(v)) >> 5) +
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(memaddr & CHIP_S_MEM_W2_MASK(v));
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} else
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#endif
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#ifdef CHIP_S_MEM_W3_START
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if (memaddr >= CHIP_S_MEM_W3_START(v) &&
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memaddr <= CHIP_S_MEM_W3_END(v)) {
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*memhp = (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W3_BASE(v)) >> 5) +
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(memaddr & CHIP_S_MEM_W3_MASK(v));
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} else
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#endif
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{
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printf("\n");
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#ifdef CHIP_S_MEM_W1_START
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printf("%s: window[1]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_mem_map)), CHIP_S_MEM_W1_START(v),
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CHIP_S_MEM_W1_END(v)-1);
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#endif
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#ifdef CHIP_S_MEM_W2_START
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printf("%s: window[2]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_mem_map)), CHIP_S_MEM_W2_START(v),
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CHIP_S_MEM_W2_END(v)-1);
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#endif
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#ifdef CHIP_S_MEM_W3_START
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printf("%s: window[3]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_mem_map)), CHIP_S_MEM_W3_START(v),
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CHIP_S_MEM_W3_END(v)-1);
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#endif
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panic("%s: don't know how to map %lx non-cacheable\n",
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__S(__C(CHIP,_mem_map)), memaddr);
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}
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}
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return (0);
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}
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void
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__C(CHIP,_mem_unmap)(v, memh, memsize)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t memsize;
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{
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/* XXX nothing to do. */
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}
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int
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__C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh)
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void *v;
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bus_mem_handle_t memh, *nmemh;
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bus_mem_size_t offset, size;
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{
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*nmemh = memh + offset;
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return (0);
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}
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u_int8_t
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__C(CHIP,_mem_read_1)(v, memh, off)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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{
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register bus_mem_handle_t tmpmemh;
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register u_int32_t *port, val;
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register u_int8_t rval;
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register int offset;
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alpha_mb();
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if ((memh >> 63) != 0)
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return (*(u_int8_t *)(memh + off));
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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port = (u_int32_t *)((tmpmemh << 5) | (0 << 3));
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val = *port;
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rval = ((val) >> (8 * offset)) & 0xff;
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return rval;
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}
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u_int16_t
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__C(CHIP,_mem_read_2)(v, memh, off)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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{
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register bus_mem_handle_t tmpmemh;
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register u_int32_t *port, val;
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register u_int16_t rval;
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register int offset;
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alpha_mb();
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if ((memh >> 63) != 0)
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return (*(u_int16_t *)(memh + off));
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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port = (u_int32_t *)((tmpmemh << 5) | (1 << 3));
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val = *port;
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rval = ((val) >> (8 * offset)) & 0xffff;
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return rval;
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}
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u_int32_t
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__C(CHIP,_mem_read_4)(v, memh, off)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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{
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register bus_mem_handle_t tmpmemh;
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register u_int32_t *port, val;
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register u_int32_t rval;
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register int offset;
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alpha_mb();
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if ((memh >> 63) != 0)
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return (*(u_int32_t *)(memh + off));
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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port = (u_int32_t *)((tmpmemh << 5) | (3 << 3));
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val = *port;
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#if 0
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rval = ((val) >> (8 * offset)) & 0xffffffff;
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#else
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rval = val;
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#endif
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return rval;
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}
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u_int64_t
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__C(CHIP,_mem_read_8)(v, memh, off)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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{
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alpha_mb();
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if ((memh >> 63) != 0)
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return (*(u_int64_t *)(memh + off));
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/* XXX XXX XXX */
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panic("%s not implemented\n", __S(__C(CHIP,_mem_read_8)));
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}
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void
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__C(CHIP,_mem_write_1)(v, memh, off, val)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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u_int8_t val;
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{
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register bus_mem_handle_t tmpmemh;
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register u_int32_t *port, nval;
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register int offset;
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if ((memh >> 63) != 0)
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(*(u_int8_t *)(memh + off)) = val;
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else {
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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nval = val << (8 * offset);
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port = (u_int32_t *)((tmpmemh << 5) | (0 << 3));
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*port = nval;
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}
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alpha_mb();
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}
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void
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__C(CHIP,_mem_write_2)(v, memh, off, val)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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u_int16_t val;
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{
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register bus_mem_handle_t tmpmemh;
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register u_int32_t *port, nval;
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register int offset;
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if ((memh >> 63) != 0)
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(*(u_int16_t *)(memh + off)) = val;
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else {
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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nval = val << (8 * offset);
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port = (u_int32_t *)((tmpmemh << 5) | (1 << 3));
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*port = nval;
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}
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alpha_mb();
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}
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void
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__C(CHIP,_mem_write_4)(v, memh, off, val)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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u_int32_t val;
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{
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register bus_mem_handle_t tmpmemh;
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register u_int32_t *port, nval;
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register int offset;
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if ((memh >> 63) != 0)
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(*(u_int32_t *)(memh + off)) = val;
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else {
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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nval = val /*<< (8 * offset)*/;
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port = (u_int32_t *)((tmpmemh << 5) | (3 << 3));
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*port = nval;
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}
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alpha_mb();
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}
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void
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__C(CHIP,_mem_write_8)(v, memh, off, val)
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void *v;
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bus_mem_handle_t memh;
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bus_mem_size_t off;
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u_int64_t val;
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{
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if ((memh >> 63) != 0)
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(*(u_int64_t *)(memh + off)) = val;
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else {
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/* XXX XXX XXX */
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panic("%s not implemented\n",
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__S(__C(CHIP,_mem_write_8)));
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}
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alpha_mb();
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}
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vm_offset_t
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__C(CHIP,_XXX_dmamap)(addr)
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void *addr;
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{
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return (vtophys((vm_offset_t)addr) | 0x40000000);
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}
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