5852faaf84
used in the SMC EtherPower II. Media control isn't yet supported, due to some MII infrastructure problems which I hope to address soon. This isn't a huge deal, since the PHY defaults to auto-negotiate mode. Also, the device just programs the multicast hash table to accept all multicast, to avoid a hardware bug that causes the multicast address filter to lose in 10Mb/s mode. This bug will be fixed in a more sane way once the media control issues are dealt with.
134 lines
4.3 KiB
C
134 lines
4.3 KiB
C
/* $NetBSD: smc83c170var.h,v 1.1 1998/06/02 01:29:42 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_SMC83C170VAR_H_
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#define _DEV_IC_SMC83C170VAR_H_
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/*
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* Misc. definitions for the Standard Microsystems Corp. 83C170
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* Ethernet PCI Integrated Controller (EPIC/100) driver.
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*/
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/*
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* Transmit descriptor list size.
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*/
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#define EPIC_NTXDESC 128
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#define EPIC_NTXDESC_MASK (EPIC_NTXDESC - 1)
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#define EPIC_NEXTTX(x) ((x + 1) & EPIC_NTXDESC_MASK)
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/*
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* Receive descriptor list size.
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*/
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#define EPIC_NRXDESC 64
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#define EPIC_NRXDESC_MASK (EPIC_NRXDESC - 1)
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#define EPIC_NEXTRX(x) ((x + 1) & EPIC_NRXDESC_MASK)
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/*
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* Control structures are DMA'd to the EPIC chip. We allocate them in
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* a single clump that maps to a single DMA segment to make several things
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* easier.
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*/
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struct epic_control_data {
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/*
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* The transmit descriptors.
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*/
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struct epic_txdesc ecd_txdescs[EPIC_NTXDESC];
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/*
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* The receive descriptors.
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*/
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struct epic_rxdesc ecd_rxdescs[EPIC_NRXDESC];
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/*
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* The transmit fraglists.
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*/
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struct epic_fraglist ecd_txfrags[EPIC_NTXDESC];
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};
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#define EPIC_CDOFF(x) offsetof(struct epic_control_data, x)
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/*
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* Software state for transmit and receive desciptors.
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*/
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struct epic_descsoft {
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struct mbuf *ds_mbuf; /* head of mbuf chain */
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bus_dmamap_t ds_dmamap; /* our DMA map */
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};
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/*
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* Software state per device.
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*/
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struct epic_softc {
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struct device sc_dev; /* generic device information */
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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bus_dma_tag_t sc_dmat; /* bus DMA tag */
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struct ethercom sc_ethercom; /* ethernet common data */
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void *sc_sdhook; /* shutdown hook */
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struct ifmedia sc_media; /* media information */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
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/*
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* Software state for transmit and receive descriptors.
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*/
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struct epic_descsoft sc_txsoft[EPIC_NTXDESC];
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struct epic_descsoft sc_rxsoft[EPIC_NRXDESC];
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/*
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* Control data structures.
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*/
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struct epic_control_data *sc_control_data;
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int sc_txpending; /* number of TX requests pending */
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int sc_txdirty; /* first dirty TX descriptor */
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int sc_txlast; /* last used TX descriptor */
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int sc_rxptr; /* next ready RX descriptor */
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};
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#ifdef _KERNEL
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void epic_attach __P((struct epic_softc *));
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int epic_intr __P((void *));
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#endif /* _KERNEL */
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#endif /* _DEV_IC_SMC83C170VAR_H_ */
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