265 lines
6.4 KiB
C
265 lines
6.4 KiB
C
typedef u_int8_t physaddr[3];
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typedef u_int8_t physlen[3];
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#define ltophys _lto3b
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#define phystol _3btol
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/*
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* I/O port offsets
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*/
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#define AHA_CTRL_PORT 0 /* control (wo) */
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#define AHA_STAT_PORT 0 /* status (ro) */
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#define AHA_CMD_PORT 1 /* command (wo) */
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#define AHA_DATA_PORT 1 /* data (ro) */
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#define AHA_INTR_PORT 2 /* interrupt status (ro) */
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/*
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* AHA_CTRL bits
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*/
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#define AHA_CTRL_HRST 0x80 /* Hardware reset */
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#define AHA_CTRL_SRST 0x40 /* Software reset */
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#define AHA_CTRL_IRST 0x20 /* Interrupt reset */
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#define AHA_CTRL_SCRST 0x10 /* SCSI bus reset */
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/*
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* AHA_STAT bits
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*/
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#define AHA_STAT_STST 0x80 /* Self test in Progress */
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#define AHA_STAT_DIAGF 0x40 /* Diagnostic Failure */
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#define AHA_STAT_INIT 0x20 /* Mbx Init required */
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#define AHA_STAT_IDLE 0x10 /* Host Adapter Idle */
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#define AHA_STAT_CDF 0x08 /* cmd/data out port full */
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#define AHA_STAT_DF 0x04 /* Data in port full */
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#define AHA_STAT_INVDCMD 0x01 /* Invalid command */
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/*
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* AHA_CMD opcodes
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*/
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#define AHA_NOP 0x00 /* No operation */
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#define AHA_MBX_INIT 0x01 /* Mbx initialization */
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#define AHA_START_SCSI 0x02 /* start scsi command */
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#define AHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */
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#define AHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */
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/*#define AHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */
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/*#define AHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */
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/*#define AHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */
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/*#define AHA_SPEED_SET 0x09 /* set transfer speed */
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#define AHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */
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#define AHA_INQUIRE_CONFIG 0x0b /* return configuration data */
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#define AHA_TARGET_EN 0x0c /* enable target mode */
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#define AHA_INQUIRE_SETUP 0x0d /* return setup data */
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#define AHA_ECHO 0x1e /* Echo command data */
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#define AHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */
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#define AHA_EXT_BIOS 0x28 /* return extended bios info */
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#define AHA_MBX_ENABLE 0x29 /* enable mail box interface */
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/*
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* AHA_INTR bits
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*/
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#define AHA_INTR_ANYINTR 0x80 /* Any interrupt */
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#define AHA_INTR_SCRD 0x08 /* SCSI reset detected */
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#define AHA_INTR_HACC 0x04 /* Command complete */
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#define AHA_INTR_MBOA 0x02 /* MBX out empty */
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#define AHA_INTR_MBIF 0x01 /* MBX in full */
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struct aha_mbx_out {
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u_char cmd;
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physaddr ccb_addr;
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};
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struct aha_mbx_in {
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u_char stat;
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physaddr ccb_addr;
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};
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/*
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* mbo.cmd values
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*/
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#define AHA_MBO_FREE 0x0 /* MBO entry is free */
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#define AHA_MBO_START 0x1 /* MBO activate entry */
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#define AHA_MBO_ABORT 0x2 /* MBO abort entry */
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/*
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* mbi.stat values
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*/
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#define AHA_MBI_FREE 0x0 /* MBI entry is free */
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#define AHA_MBI_OK 0x1 /* completed without error */
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#define AHA_MBI_ABORT 0x2 /* aborted ccb */
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#define AHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */
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#define AHA_MBI_ERROR 0x4 /* Completed with error */
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/* FOR OLD VERSIONS OF THE !%$@ this may have to be 16 (yuk) */
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#define AHA_NSEG 17 /* Number of scatter gather segments <= 16 */
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/* allow 64 K i/o (min) */
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struct aha_scat_gath {
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physlen seg_len;
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physaddr seg_addr;
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};
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struct aha_ccb {
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u_char opcode;
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u_char lun:3;
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u_char data_in:1; /* must be 0 */
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u_char data_out:1; /* must be 0 */
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u_char target:3;
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u_char scsi_cmd_length;
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u_char req_sense_length;
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physlen data_length;
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physaddr data_addr;
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physaddr link_addr;
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u_char link_id;
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u_char host_stat;
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u_char target_stat;
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u_char reserved[2];
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struct scsi_generic scsi_cmd;
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struct scsi_sense_data scsi_sense;
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struct aha_scat_gath scat_gath[AHA_NSEG];
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/*----------------------------------------------------------------*/
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TAILQ_ENTRY(aha_ccb) chain;
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struct aha_ccb *nexthash;
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long hashkey;
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struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
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int flags;
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#define CCB_ALLOC 0x01
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#define CCB_ABORT 0x02
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#ifdef AHADIAG
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#define CCB_SENDING 0x04
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#endif
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int timeout;
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};
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/*
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* opcode fields
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*/
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#define AHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */
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#define AHA_TARGET_CCB 0x01 /* SCSI Target CCB */
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#define AHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scatter gather */
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#define AHA_RESET_CCB 0x81 /* SCSI Bus reset */
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/*
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* aha_ccb.host_stat values
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*/
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#define AHA_OK 0x00 /* cmd ok */
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#define AHA_LINK_OK 0x0a /* Link cmd ok */
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#define AHA_LINK_IT 0x0b /* Link cmd ok + int */
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#define AHA_SEL_TIMEOUT 0x11 /* Selection time out */
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#define AHA_OVER_UNDER 0x12 /* Data over/under run */
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#define AHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */
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#define AHA_INV_BUS 0x14 /* Invalid bus phase/sequence */
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#define AHA_BAD_MBO 0x15 /* Incorrect MBO cmd */
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#define AHA_BAD_CCB 0x16 /* Incorrect ccb opcode */
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#define AHA_BAD_LINK 0x17 /* Not same values of LUN for links */
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#define AHA_INV_TARGET 0x18 /* Invalid target direction */
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#define AHA_CCB_DUP 0x19 /* Duplicate CCB received */
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#define AHA_INV_CCB 0x1a /* Invalid CCB or segment list */
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struct aha_revision {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char boardid; /* type of board */
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/* 0x31 = AHA-1540 */
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/* 0x41 = AHA-1540A/1542A/1542B */
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/* 0x42 = AHA-1640 */
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/* 0x43 = AHA-1542C */
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/* 0x44 = AHA-1542CF */
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/* 0x45 = AHA-1542CF, BIOS v2.01 */
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/* 0x46 = AHA-1542CP */
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u_char spec_opts; /* special options ID */
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/* 0x41 = Board is standard model */
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u_char revision_1; /* firmware revision [0-9A-Z] */
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u_char revision_2; /* firmware revision [0-9A-Z] */
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} reply;
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};
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struct aha_extbios {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char flags; /* Bit 3 == 1 extended bios enabled */
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u_char mailboxlock; /* mail box lock code to unlock it */
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} reply;
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};
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struct aha_toggle {
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struct {
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u_char opcode;
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u_char enable;
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} cmd;
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};
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struct aha_config {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char chan;
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u_char intr;
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u_char scsi_dev:3;
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u_char :5;
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} reply;
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};
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struct aha_mailbox {
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struct {
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u_char opcode;
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u_char nmbx;
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physaddr addr;
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} cmd;
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};
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struct aha_unlock {
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struct {
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u_char opcode;
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u_char junk;
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u_char magic;
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} cmd;
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};
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struct aha_devices {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char junk[8];
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} reply;
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};
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struct aha_setup {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct {
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u_char sync_neg:1;
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u_char parity:1;
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u_char :6;
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u_char speed;
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u_char bus_on;
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u_char bus_off;
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u_char num_mbx;
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u_char mbx[3];
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struct {
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u_char offset:4;
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u_char period:3;
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u_char valid:1;
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} sync[8];
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u_char disc_sts;
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} reply;
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};
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#define INT9 0x01
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#define INT10 0x02
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#define INT11 0x04
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#define INT12 0x08
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#define INT14 0x20
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#define INT15 0x40
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#define EISADMA 0x00
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#define CHAN0 0x01
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#define CHAN5 0x20
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#define CHAN6 0x40
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#define CHAN7 0x80
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