a534631ee7
with []. Using the driver with my Linksys WPC11 ver. 4, it seems to be receiving packets for a change. The WPC11 ver. 4 has a Maxim RF section. My no-name rtw with Philips RF section still does not receive any packets. Keep access-level (analog params > config[0123] registers > none) in sc_access. Add rtw_set_access for changing the access level. Make rtw_continuous_tx_enable and other subroutines use rtw_set_access instead of rtw_config0123_enable and rtw_anaparm_enable. Factor part of the chip-reset code into rtw_chip_reset1. Change the 'struct foo (*bar)[N]'-style arguments to 'struct foo *bar'-style arguments. Consolidate software/hardware Tx/Rx ring setup in rtw_hwring_setup, rtw_swring_setup. Add a new constant, SA2400_OPMODE_DEFAULTS, for the bits that we *always* set in the SA2400 OPMODE register. Factor some code out into rtw_sa2400_calibrate. (Inspired by the Linux driver.) [] When the receiver goes into underrun/overflow state, call a new subroutine, rtw_kick() that stops the Rx/Tx processes, resets the chip, reinitializes the Tx/Rx rings, and restarts Rx/Tx processes. (Inspired by the Linux driver.) [] In rtw_intr_rx, check for too-short packets before calling ieee80211_find_rxnode. I believe this will prevent a repeat of the MCHK exception I saw once on macppc. [] Use seconds-elapased as well as microseconds-elapsed to set the next "due date" for the timeout interrupt. This keeps the driver from programming the timeout to expire too early. [] In rtw_intr, read RTW_ISR at most 10 times, then get out. If the interface is not enabled (RTW_F_ENABLED), then get out. [] In rtw_stop, get out if the interface is not enabled (RTW_F_ENABLED). Block IPL_NET interrupts. Don't read/write any registers if the interface is invalid (RTW_F_INVALID). [] Call rtw_stop in rtw_detach.
263 lines
9.7 KiB
C
263 lines
9.7 KiB
C
/* $NetBSD: sa2400reg.h,v 1.2 2004/12/12 06:37:59 dyoung Exp $ */
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/*
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* Copyright (c) 2005 David Young. All rights reserved.
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*
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* This code was written by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
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* Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_SA2400REG_H_
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#define _DEV_IC_SA2400REG_H_
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/*
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* Serial bus format for Philips SA2400 Single-chip Transceiver.
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*/
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#define SA2400_TWI_DATA_MASK BITS(31,8)
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#define SA2400_TWI_WREN BIT(7) /* enable write */
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#define SA2400_TWI_ADDR_MASK BITS(6,0)
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/*
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* Registers for Philips SA2400 Single-chip Transceiver.
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*/
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#define SA2400_SYNA 0 /* Synthesizer Register A */
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#define SA2400_SYNA_FM BIT(21) /* fractional modulus select,
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* 0: /8 (default)
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* 1: /5
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*/
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#define SA2400_SYNA_NF_MASK BITS(20,18) /* fractional increment value,
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* 0 to 7, default 4
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*/
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#define SA2400_SYNA_N_MASK BITS(17,2) /* main divider division ratio,
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* 512 to 65535, default 615
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*/
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#define SA2400_SYNB 1 /* Synthesizer Register B */
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#define SA2400_SYNB_R_MASK BITS(21,12) /* reference divider ratio,
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* 4 to 1023, default 11
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*/
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#define SA2400_SYNB_L_MASK BITS(11,10) /* lock detect mode */
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#define SA2400_SYNB_L_INACTIVE0 LSHIFT(0, SA2400_SYNB_L_MASK)
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#define SA2400_SYNB_L_INACTIVE1 LSHIFT(1, SA2400_SYNB_L_MASK)
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#define SA2400_SYNB_L_NORMAL LSHIFT(2, SA2400_SYNB_L_MASK)
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#define SA2400_SYNB_L_INACTIVE2 LSHIFT(3, SA2400_SYNB_L_MASK)
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#define SA2400_SYNB_ON BIT(9) /* power on/off,
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* 0: inverted chip mode control
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* 1: as defined by chip mode
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* (see SA2400_OPMODE)
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*/
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#define SA2400_SYNB_ONE BIT(8) /* always 1 */
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#define SA2400_SYNB_FC_MASK BITS(7,0) /* fractional compensation
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* charge pump current DAC,
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* 0 to 255, default 80.
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*/
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#define SA2400_SYNC 2 /* Synthesizer Register C */
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#define SA2400_SYNC_CP_MASK BITS(7,6) /* charge pump current
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* setting
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*/
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#define SA2400_SYNC_CP_NORMAL_ LSHIFT(0, SA2400_SYNC_CP_MASK)
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#define SA2400_SYNC_CP_THIRD_ LSHIFT(1, SA2400_SYNC_CP_MASK)
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#define SA2400_SYNC_CP_NORMAL LSHIFT(2, SA2400_SYNC_CP_MASK) /* recommended */
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#define SA2400_SYNC_CP_THIRD LSHIFT(3, SA2400_SYNC_CP_MASK)
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#define SA2400_SYNC_SM_MASK BITS(5,3) /* comparison divider select,
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* 0 to 4, extra division
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* ratio is 2**SM.
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*/
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#define SA2400_SYNC_ZERO BIT(2) /* always 0 */
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#define SA2400_SYND 3 /* Synthesizer Register D */
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#define SA2400_SYND_ZERO1_MASK BITS(21,17) /* always 0 */
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#define SA2400_SYND_TPHPSU BIT(16) /* T[phpsu], 1: disable
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* PHP speedup pump,
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* overrides SA2400_SYND_TSPU
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*/
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#define SA2400_SYND_TPSU BIT(15) /* T[spu], 1: speedup on,
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* 0: speedup off
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*/
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#define SA2400_SYND_ZERO2_MASK BITS(14,3) /* always 0 */
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#define SA2400_OPMODE 4 /* Operating mode, filter tuner,
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* other controls
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*/
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#define SA2400_OPMODE_ADC BIT(19) /* 1: in Rx mode, RSSI-ADC always on
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* 0: RSSI-ADC only on during AGC
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*/
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#define SA2400_OPMODE_FTERR BIT(18) /* read-only filter tuner error:
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* 1 if tuner out of range
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*/
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/* Rx & Tx filter tuning, write tuning value (test mode only) or
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* read tuner setting (in normal mode).
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*/
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#define SA2400_OPMODE_FILTTUNE_MASK BITS(17,15)
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#define SA2400_OPMODE_V2P5 BIT(14) /* external reference voltage
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* (pad v2p5) on
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*/
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#define SA2400_OPMODE_I1M BIT(13) /* external reference current ... */
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#define SA2400_OPMODE_I0P3 BIT(12) /* external reference current ... */
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#define SA2400_OPMODE_IN22 BIT(10) /* xtal input frequency,
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* 0: 44 MHz
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* 1: 22 MHz
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*/
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#define SA2400_OPMODE_CLK BIT(9) /* reference clock output on */
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#define SA2400_OPMODE_XO BIT(8) /* xtal oscillator on */
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#define SA2400_OPMODE_DIGIN BIT(7) /* use digital Tx inputs (FIRDAC) */
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#define SA2400_OPMODE_RXLV BIT(6) /* Rx output common mode voltage,
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* 0: V[DD]/2
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* 1: 1.25V
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*/
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#define SA2400_OPMODE_VEO BIT(5) /* make internal vco
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* available at vco pads (vcoextout)
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*/
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#define SA2400_OPMODE_VEI BIT(4) /* use external vco input (vcoextin) */
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/* main operating mode */
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#define SA2400_OPMODE_MODE_MASK BITS(3,0)
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#define SA2400_OPMODE_MODE_SLEEP LSHIFT(0, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_MODE_TXRX LSHIFT(1, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_MODE_WAIT LSHIFT(2, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_MODE_RXMGC LSHIFT(3, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_MODE_FCALIB LSHIFT(4, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_MODE_DCALIB LSHIFT(5, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_MODE_FASTTXRXMGC LSHIFT(6, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_MODE_RESET LSHIFT(7, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_MODE_VCOCALIB LSHIFT(8, SA2400_OPMODE_MODE_MASK)
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#define SA2400_OPMODE_DEFAULTS \
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(SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK | \
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SA2400_OPMODE_I0P3 | LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK))
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#define SA2400_AGC 5 /* AGC adjustment */
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#define SA2400_AGC_TARGETSIGN BIT(23) /* fine-tune AGC target:
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* -7dB to 7dB, sign bit ... */
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#define SA2400_AGC_TARGET_MASK BITS(22,20) /* ... plus 0dB - 7dB */
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#define SA2400_AGC_MAXGAIN_MASK BITS(19,15) /* maximum AGC gain, 0 to 31,
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* (yields 54dB to 85dB)
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*/
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/* write: settling time after baseband gain switching, units of
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* 182 nanoseconds.
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* read: output of RSSI/Tx-peak detector's ADC in 5-bit Gray code.
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*/
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#define SA2400_AGC_BBPDELAY_MASK BITS(14,10)
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#define SA2400_AGC_ADCVAL_MASK SA2400_AGC_BBPDELAY_MASK
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/* write: settling time after LNA gain switching, units of
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* 182 nanoseconds
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* read: 2nd sample of RSSI in AGC cycle
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*/
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#define SA2400_AGC_LNADELAY_MASK BITS(9,5)
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#define SA2400_AGC_SAMPLE2_MASK SA2400_AGC_LNADELAY_MASK
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/* write: time between turning on Rx and AGCSET, units of
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* 182 nanoseconds
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* read: 1st sample of RSSI in AGC cycle
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*/
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#define SA2400_AGC_RXONDELAY_MASK BITS(4,0)
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#define SA2400_AGC_SAMPLE1_MASK SA2400_AGC_RXONDELAY_MASK
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#define SA2400_MANRX 6 /* Manual receiver control settings */
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#define SA2400_MANRX_AHSN BIT(23) /* 1: AGC w/ high S/N---switch LNA at
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* step 52 (recommended)
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* 0: switch LNA at step 60
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*/
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/* If _RXOSQON, Q offset is
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* (_RXOSQSIGN ? -1 : 1) * (1 + _RXOSQ_MASK) * 8 millivolts,
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* otherwise, Q offset is 0.
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*
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* Ditto I offset.
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*/
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#define SA2400_MANRX_RXOSQON BIT(22) /* Rx Q-channel correction. */
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#define SA2400_MANRX_RXOSQSIGN BIT(21)
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#define SA2400_MANRX_RXOSQ_MASK BITS(20,18)
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#define SA2400_MANRX_RXOSION BIT(17) /* Rx I-channel correction. */
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#define SA2400_MANRX_RXOSISIGN BIT(16)
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#define SA2400_MANRX_RXOSI_MASK BITS(15,13)
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#define SA2400_MANRX_TEN BIT(12) /* use 10MHz offset cancellation
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* cornerpoint for brief period
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* after each gain change
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*/
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/* DC offset cancellation cornerpoint select
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* write: in RXMGC, set the cornerpoint
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* read: in other modes, read AGC-controlled cornerpoint
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*/
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#define SA2400_MANRX_CORNERFREQ_MASK BITS(11,10)
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/* write: in RXMGC mode, sets receiver gain
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* read: in other modes, read AGC-controlled gain
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*/
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#define SA2400_MANRX_RXGAIN_MASK BITS(9,0)
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#define SA2400_TX 7 /* Transmitter settings */
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/* Tx offsets
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*
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* write: in test mode, sets the offsets
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* read: in normal mode, returns automatic settings
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*/
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#define SA2400_TX_TXOSQON BIT(19)
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#define SA2400_TX_TXOSQSIGN BIT(18)
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#define SA2400_TX_TXOSQ_MASK BITS(17,15)
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#define SA2400_TX_TXOSION BIT(14)
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#define SA2400_TX_TXOSISIGN BIT(13)
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#define SA2400_TX_TXOSI_MASK BITS(12,10)
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#define SA2400_TX_RAMP_MASK BITS(9,8) /* Ramp-up delay,
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* 0: 1us
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* 1: 2us
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* 2: 3us
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* 3: 4us
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* datasheet says, "ramp-up
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* time always 1us". huh?
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*/
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#define SA2400_TX_HIGAIN_MASK BITS(7,4) /* Transmitter gain settings
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* for TXHI output
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*/
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#define SA2400_TX_LOGAIN_MASK BITS(3,0) /* Transmitter gain settings
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* for TXLO output
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*/
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#define SA2400_VCO 8 /* VCO settings */
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#define SA2400_VCO_ZERO BITS(6,5) /* always zero */
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#define SA2400_VCO_VCERR BIT(4) /* VCO calibration error flag---no
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* band with low enough frequency
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* could be found
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*/
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#define SA2400_VCO_VCOBAND_MASK BITS(3,0) /* VCO band,
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* write: in test mode, sets
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* VCO band
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* read: in normal mode,
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* the result of
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* calibration (VCOCAL).
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* 0 = highest
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* frequencies
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*/
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#endif /* _DEV_IC_SA2400REG_H_ */
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