164 lines
5.0 KiB
C
164 lines
5.0 KiB
C
/* $NetBSD: mcontext.h,v 1.10 2008/10/26 06:58:02 mrg Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Klaus Klein.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SPARC_MCONTEXT_H_
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#define _SPARC_MCONTEXT_H_
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#define _UC_SETSTACK 0x00010000
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#define _UC_CLRSTACK 0x00020000
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/*
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* Layout of mcontext_t according the System V Application Binary Interface,
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* Edition 4.1, SPARC Processor ABI Supplement and updated for SPARC v9.
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*/
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#ifdef __arch64__
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#define _NGREG 21 /* %ccr, pc, npc, %g1-7, %o0-7, %asi, %fprs */
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#else
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#define _NGREG 19 /* %psr, pc, npc, %g1-7, %o0-7 */
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#endif
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typedef long int __greg_t;
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typedef __greg_t __gregset_t[_NGREG];
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/* Offsets into gregset_t, for convenience. */
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#define _REG_CCR 0 /* 64 bit only */
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#define _REG_PSR 0 /* 32 bit only */
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#define _REG_PC 1
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#define _REG_nPC 2
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#define _REG_Y 3
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#define _REG_G1 4
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#define _REG_G2 5
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#define _REG_G3 6
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#define _REG_G4 7
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#define _REG_G5 8
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#define _REG_G6 9
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#define _REG_G7 10
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#define _REG_O0 11
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#define _REG_O1 12
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#define _REG_O2 13
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#define _REG_O3 14
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#define _REG_O4 15
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#define _REG_O5 16
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#define _REG_O6 17
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#define _REG_O7 18
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#define _REG_ASI 19 /* 64 bit only */
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#define _REG_FPRS 20 /* 64 bit only */
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#define _SPARC_MAXREGWINDOW 31
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/* Layout of a register window. */
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typedef struct {
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__greg_t __rw_local[8]; /* %l0-7 */
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__greg_t __rw_in[8]; /* %i0-7 */
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} __rwindow_t;
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/* Description of available register windows. */
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typedef struct {
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int __wbcnt;
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__greg_t * __spbuf[_SPARC_MAXREGWINDOW];
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__rwindow_t __wbuf[_SPARC_MAXREGWINDOW];
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} __gwindows_t;
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/* FPU address queue */
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struct __fpq {
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unsigned int * __fpq_addr; /* address */
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unsigned int __fpq_instr; /* instruction */
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};
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struct __fq {
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union {
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double __whole;
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struct __fpq __fpq;
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} _FQu;
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};
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/* FPU state description */
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typedef struct {
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union {
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unsigned int __fpu_regs[32];
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#ifdef __arch64__
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double __fpu_dregs[32];
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long double __fpu_qregs[16];
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#else
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double __fpu_dregs[16];
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#endif
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} __fpu_fr; /* FPR contents */
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struct __fq * __fpu_q; /* pointer to FPU insn queue */
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unsigned long __fpu_fsr; /* %fsr */
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unsigned char __fpu_qcnt; /* # entries in __fpu_q */
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unsigned char __fpu_q_entrysize; /* size of a __fpu_q entry */
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unsigned char __fpu_en; /* this context valid? */
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} __fpregset_t;
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/* `Extra Register State'(?) */
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typedef struct {
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unsigned int __xrs_id; /* See below */
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char * __xrs_ptr; /* points into filler area */
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} __xrs_t;
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#define _XRS_ID 0x78727300 /* 'xrs\0' */
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#ifdef __arch64__
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/* Ancillary State Registers, 16-31 are available to user programs */
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typedef long __asrset_t[16]; /* %asr16-31 */
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#endif
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typedef struct {
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__gregset_t __gregs; /* GPR state */
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__gwindows_t * __gwins; /* may point to register windows */
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__fpregset_t __fpregs; /* FPU state, if any */
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__xrs_t __xrs; /* may indicate extra reg state */
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#ifdef __arch64__
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__asrset_t __asrs; /* ASR state */
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#endif
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} mcontext_t;
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#ifdef __arch64__
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#define _UC_MACHINE_PAD 8 /* Padding appended to ucontext_t */
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#define _UC_MACHINE_SP(uc) (((uc)->uc_mcontext.__gregs[_REG_O6])+0x7ff)
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#define _UC_MACHINE32_PAD 43 /* compat_netbsd32 variant */
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#define _UC_MACHINE32_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_O6])
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#else
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#define _UC_MACHINE_PAD 43 /* Padding appended to ucontext_t */
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#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_O6])
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#endif
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#define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_PC])
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#define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_O0])
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#define _UC_MACHINE_SET_PC(uc, pc) \
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do { \
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(uc)->uc_mcontext.__gregs[_REG_PC] = (pc); \
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(uc)->uc_mcontext.__gregs[_REG_nPC] = (pc) + 4; \
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} while (/*CONSTCOND*/0)
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#endif /* !_SPARC_MCONTEXT_H_ */
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