88 lines
3.2 KiB
C
88 lines
3.2 KiB
C
/* $NetBSD: sa11x0_dmacreg.h,v 1.3 2008/04/28 20:23:14 martin Exp $ */
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/*-
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* Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by IWAMOTO Toshihiro.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* SA11[01]0 integrated DMA controller */
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#define SADMAC_NPORTS 40
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#define SADMAC_DAR0 0x00 /* DMA device address register */
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#define SADMAC_DCR0_SET 0x04 /* DMA control/status (set) */
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#define SADMAC_DCR0_CLR 0x08 /* DMA control/status (clear) */
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#define SADMAC_DCR0 0x0C /* DMA control/status (read only) */
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#define SADMAC_DBSA0 0x10 /* DMA Buffer A start address */
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#define SADMAC_DBTA0 0x14 /* DMA Buffer A transfer count */
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#define SADMAC_DBSB0 0x18 /* DMA Buffer B start address */
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#define SADMAC_DBTB0 0x1C /* DMA Buffer B transfer count */
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#define SADMAC_DAR1 0x20
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#define SADMAC_DCR1_SET 0x24
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#define SADMAC_DCR1_CLR 0x28
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#define SADMAC_DCR1 0x2C
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#define SADMAC_DBSA1 0x30
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#define SADMAC_DBTA1 0x34
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#define SADMAC_DBSB1 0x38
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#define SADMAC_DBTB1 0x3C
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#define SADMAC_DAR2 0x40
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#define SADMAC_DCR2_SET 0x44
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#define SADMAC_DCR2_CLR 0x48
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#define SADMAC_DCR2 0x4C
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#define SADMAC_DBSA2 0x50
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#define SADMAC_DBTA2 0x54
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#define SADMAC_DBSB2 0x58
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#define SADMAC_DBTB2 0x5C
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#define SADMAC_DAR3 0x60
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#define SADMAC_DCR3_SET 0x64
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#define SADMAC_DCR3_CLR 0x68
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#define SADMAC_DCR3 0x6C
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#define SADMAC_DBSA3 0x70
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#define SADMAC_DBTA3 0x74
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#define SADMAC_DBSB3 0x78
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#define SADMAC_DBTB3 0x7C
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#define SADMAC_DAR4 0x80
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#define SADMAC_DCR4_SET 0x84
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#define SADMAC_DCR4_CLR 0x88
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#define SADMAC_DCR4 0x8C
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#define SADMAC_DBSA4 0x90
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#define SADMAC_DBTA4 0x94
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#define SADMAC_DBSB4 0x98
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#define SADMAC_DBTB4 0x9C
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#define SADMAC_DAR5 0xA0
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#define SADMAC_DCR5_SET 0xA4
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#define SADMAC_DCR5_CLR 0xA8
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#define SADMAC_DCR5 0xAC
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#define SADMAC_DBSA5 0xB0
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#define SADMAC_DBTA5 0xB4
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#define SADMAC_DBSB5 0xB8
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#define SADMAC_DBTB5 0xBC
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