203 lines
7.5 KiB
C
203 lines
7.5 KiB
C
/* $NetBSD: wdcreg.h,v 1.17 1998/04/26 05:28:24 mycroft Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)wdreg.h 7.1 (Berkeley) 5/9/91
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*/
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/*
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* Disk Controller register definitions.
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*/
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/* offsets of registers in the 'regular' register region */
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#define wd_data 0 /* data register (R/W - 16 bits) */
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#define wd_error 1 /* error register (R) */
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#define wd_precomp 1 /* write precompensation (W) */
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#define wd_features 1 /* features (W) */
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#define wd_seccnt 2 /* sector count (R/W) */
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#define wd_ireason 2 /* interrupt reason (R/W) (for atapi) */
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#define wd_sector 3 /* first sector number (R/W) */
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#define wd_cyl_lo 4 /* cylinder address, low byte (R/W) */
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#define wd_cyl_hi 5 /* cylinder address, high byte (R/W) */
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#define wd_sdh 6 /* sector size/drive/head (R/W) */
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#define wd_command 7 /* command register (W) */
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#define wd_status 7 /* immediate status (R) */
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/* offsets of registers in the auxiliary register region */
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#define wd_aux_altsts 0 /* alternate fixed disk status (R) */
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#define wd_aux_ctlr 0 /* fixed disk controller control (W) */
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#define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */
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#define WDCTL_RST 0x04 /* reset the controller */
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#define WDCTL_IDS 0x02 /* disable controller interrupts */
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#if 0 /* NOT MAPPED; fd uses this register on PCs */
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#define wd_digin 1 /* disk controller input (R) */
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#endif
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/*
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* Status bits.
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*/
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#define WDCS_BSY 0x80 /* busy */
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#define WDCS_DRDY 0x40 /* drive ready */
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#define WDCS_DWF 0x20 /* drive write fault */
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#define WDCS_DSC 0x10 /* drive seek complete */
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#define WDCS_DRQ 0x08 /* data request */
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#define WDCS_CORR 0x04 /* corrected data */
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#define WDCS_IDX 0x02 /* index */
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#define WDCS_ERR 0x01 /* error */
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#define WDCS_BITS "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err"
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/*
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* Error bits.
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*/
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#define WDCE_BBK 0x80 /* bad block detected */
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#define WDCE_UNC 0x40 /* uncorrectable data error */
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#define WDCE_MC 0x20 /* media changed */
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#define WDCE_IDNF 0x10 /* id not found */
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#define WDCE_MCR 0x08 /* media change requested */
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#define WDCE_ABRT 0x04 /* aborted command */
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#define WDCE_TK0NF 0x02 /* track 0 not found */
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#define WDCE_AMNF 0x01 /* address mark not found */
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#define WDERR_BITS "\020\010bbk\007unc\006mc\005idnf\004mcr\003abrt\002tk0nf\001amnf"
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/*
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* Commands for Disk Controller.
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*/
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#define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */
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#define WDCC_READ 0x20 /* disk read code */
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#define WDCC_WRITE 0x30 /* disk write code */
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#define WDCC__LONG 0x02 /* modifier -- access ecc bytes */
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#define WDCC__NORETRY 0x01 /* modifier -- no retrys */
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#define WDCC_FORMAT 0x50 /* disk format code */
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#define WDCC_DIAGNOSE 0x90 /* controller diagnostic */
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#define WDCC_IDP 0x91 /* initialize drive parameters */
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#define WDCC_READMULTI 0xc4 /* read multiple */
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#define WDCC_WRITEMULTI 0xc5 /* write multiple */
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#define WDCC_SETMULTI 0xc6 /* set multiple mode */
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#define WDCC_READDMA 0xc8 /* read with DMA */
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#define WDCC_WRITEDMA 0xca /* write with DMA */
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#define WDCC_ACKMC 0xdb /* acknowledge media change */
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#define WDCC_LOCK 0xde /* lock drawer */
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#define WDCC_UNLOCK 0xdf /* unlock drawer */
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#define WDCC_IDENTIFY 0xec /* read parameters from controller */
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#define WDCC_CACHEC 0xef /* cache control */
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#define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */
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#define WDSD_CHS 0x00 /* cylinder/head/sector addressing */
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#define WDSD_LBA 0x40 /* logical block addressing */
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/* Commands for ATAPI devices */
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#define ATAPI_CHECK_POWER_MODE 0xe5
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#define ATAPI_EXEC_DRIVE_DIAGS 0x90
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#define ATAPI_IDLE_IMMEDIATE 0xe1
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#define ATAPI_NOP 0x00
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#define ATAPI_PACKET_COMMAND 0xa0
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#define ATAPI_IDENTIFY_DEVICE 0xa1
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#define ATAPI_SOFT_RESET 0x08
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#define ATAPI_SET_FEATURES 0xef
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#define ATAPI_SLEEP 0xe6
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#define ATAPI_STANDBY_IMMEDIATE 0xe0
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/* ireason */
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#define WDCI_CMD 0x01 /* command(1) or data(0) */
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#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */
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#define WDCI_RELEASE 0x04 /* bus released until completion */
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#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD)
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#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN)
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#define PHASE_DATAOUT WDCS_DRQ
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#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD)
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#define PHASE_ABORTED 0
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#ifdef _KERNEL
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/*
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* read parameters command returns this:
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*/
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struct wdparams {
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/* drive info */
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u_short wdp_config; /* general configuration */
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#define WD_CFG_REMOVABLE 0x0080
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#define WD_CFG_FIXED 0x0040
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u_short wdp_cylinders; /* number of non-removable cylinders */
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u_short __reserved1;
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u_short wdp_heads; /* number of heads */
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u_short __retired1[2]; /* number of unformatted bytes/track */
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u_short wdp_sectors; /* number of sectors */
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u_short __retired2[3];
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char wdp_serial[20]; /* serial number */
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u_short __retired3[2];
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u_short __obsolete1;
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char wdp_revision[8]; /* firmware revision */
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char wdp_model[40]; /* model name */
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u_short wdp_multi; /* maximum sectors per interrupt */
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u_short __reserved2;
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u_short wdp_capabilities1; /* capability flags */
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#define WD_CAP_LBA 0x0200
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#define WD_CAP_DMA 0x0100
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u_short wdp_capabilities2;
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char __junk2;
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char wdp_oldpiotiming; /* PIO timing mode */
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char __junk3;
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char wdp_olddmatiming; /* DMA timing mode */
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u_short wdp_extensions;
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u_short wdp_curcylinders;
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u_short wdp_curheads;
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u_short wdp_cursectors;
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u_short wdp_curcapacity[2];
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u_short wdp_curmulti;
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u_short wdp_capacity[2];
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u_short __retired4;
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u_short wdp_dmamode;
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u_short wdp_piomode;
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u_short wdp_dmatiming[2];
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u_short wdp_piotiming[2];
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u_short __reserved3[6];
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u_short wdp_queuedepth;
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u_short __reserved4[4];
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u_short wdp_ataversion;
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#define WD_VER_ATA1 0x0002
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#define WD_VER_ATA2 0x0004
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#define WD_VER_ATA3 0x0008
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#define WD_VER_ATA4 0x0010
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};
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#endif /* _KERNEL */
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