337 lines
11 KiB
C
337 lines
11 KiB
C
/* $NetBSD: pcireg.h,v 1.19 1998/12/21 20:31:54 drochner Exp $ */
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/*
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* Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_PCIREG_H_
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#define _DEV_PCI_PCIREG_H_
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/*
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* Standardized PCI configuration information
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*
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* XXX This is not complete.
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*/
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/*
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* Device identification register; contains a vendor ID and a device ID.
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*/
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#define PCI_ID_REG 0x00
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typedef u_int16_t pci_vendor_id_t;
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typedef u_int16_t pci_product_id_t;
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#define PCI_VENDOR_SHIFT 0
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#define PCI_VENDOR_MASK 0xffff
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#define PCI_VENDOR(id) \
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(((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
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#define PCI_PRODUCT_SHIFT 16
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#define PCI_PRODUCT_MASK 0xffff
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#define PCI_PRODUCT(id) \
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(((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
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/*
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* Command and status register.
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*/
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#define PCI_COMMAND_STATUS_REG 0x04
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#define PCI_COMMAND_IO_ENABLE 0x00000001
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#define PCI_COMMAND_MEM_ENABLE 0x00000002
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#define PCI_COMMAND_MASTER_ENABLE 0x00000004
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#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
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#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
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#define PCI_COMMAND_PALETTE_ENABLE 0x00000020
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#define PCI_COMMAND_PARITY_ENABLE 0x00000040
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#define PCI_COMMAND_STEPPING_ENABLE 0x00000080
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#define PCI_COMMAND_SERR_ENABLE 0x00000100
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#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
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#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
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#define PCI_STATUS_66MHZ_SUPPORT 0x00200000
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#define PCI_STATUS_UDF_SUPPORT 0x00400000
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#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
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#define PCI_STATUS_PARITY_ERROR 0x01000000
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#define PCI_STATUS_DEVSEL_FAST 0x00000000
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#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
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#define PCI_STATUS_DEVSEL_SLOW 0x04000000
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#define PCI_STATUS_DEVSEL_MASK 0x06000000
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#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
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#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
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#define PCI_STATUS_MASTER_ABORT 0x20000000
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#define PCI_STATUS_SPECIAL_ERROR 0x40000000
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#define PCI_STATUS_PARITY_DETECT 0x80000000
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/*
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* PCI Class and Revision Register; defines type and revision of device.
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*/
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#define PCI_CLASS_REG 0x08
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typedef u_int8_t pci_class_t;
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typedef u_int8_t pci_subclass_t;
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typedef u_int8_t pci_interface_t;
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typedef u_int8_t pci_revision_t;
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#define PCI_CLASS_SHIFT 24
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#define PCI_CLASS_MASK 0xff
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#define PCI_CLASS(cr) \
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(((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
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#define PCI_SUBCLASS_SHIFT 16
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#define PCI_SUBCLASS_MASK 0xff
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#define PCI_SUBCLASS(cr) \
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(((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
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#define PCI_INTERFACE_SHIFT 8
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#define PCI_INTERFACE_MASK 0xff
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#define PCI_INTERFACE(cr) \
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(((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
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#define PCI_REVISION_SHIFT 0
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#define PCI_REVISION_MASK 0xff
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#define PCI_REVISION(cr) \
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(((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
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/* base classes */
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#define PCI_CLASS_PREHISTORIC 0x00
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#define PCI_CLASS_MASS_STORAGE 0x01
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#define PCI_CLASS_NETWORK 0x02
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#define PCI_CLASS_DISPLAY 0x03
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#define PCI_CLASS_MULTIMEDIA 0x04
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#define PCI_CLASS_MEMORY 0x05
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#define PCI_CLASS_BRIDGE 0x06
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#define PCI_CLASS_COMMUNICATIONS 0x07
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#define PCI_CLASS_SYSTEM 0x08
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#define PCI_CLASS_INPUT 0x09
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#define PCI_CLASS_DOCK 0x0a
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#define PCI_CLASS_PROCESSOR 0x0b
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#define PCI_CLASS_SERIALBUS 0x0c
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#define PCI_CLASS_UNDEFINED 0xff
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/* 0x00 prehistoric subclasses */
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#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
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#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
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/* 0x01 mass storage subclasses */
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#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
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#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
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#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
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#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
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#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
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#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
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/* 0x02 network subclasses */
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#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
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#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
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#define PCI_SUBCLASS_NETWORK_FDDI 0x02
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#define PCI_SUBCLASS_NETWORK_ATM 0x03
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#define PCI_SUBCLASS_NETWORK_MISC 0x80
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/* 0x03 display subclasses */
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#define PCI_SUBCLASS_DISPLAY_VGA 0x00
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#define PCI_SUBCLASS_DISPLAY_XGA 0x01
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#define PCI_SUBCLASS_DISPLAY_MISC 0x80
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/* 0x04 multimedia subclasses */
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#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
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#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
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#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
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/* 0x05 memory subclasses */
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#define PCI_SUBCLASS_MEMORY_RAM 0x00
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#define PCI_SUBCLASS_MEMORY_FLASH 0x01
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#define PCI_SUBCLASS_MEMORY_MISC 0x80
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/* 0x06 bridge subclasses */
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#define PCI_SUBCLASS_BRIDGE_HOST 0x00
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#define PCI_SUBCLASS_BRIDGE_ISA 0x01
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#define PCI_SUBCLASS_BRIDGE_EISA 0x02
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#define PCI_SUBCLASS_BRIDGE_MC 0x03
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#define PCI_SUBCLASS_BRIDGE_PCI 0x04
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#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
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#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
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#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
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#define PCI_SUBCLASS_BRIDGE_MISC 0x80
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/* 0x07 communications subclasses */
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#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
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#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
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#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
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/* 0x08 system subclasses */
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#define PCI_SUBCLASS_SYSTEM_PIC 0x00
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#define PCI_SUBCLASS_SYSTEM_DMA 0x01
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#define PCI_SUBCLASS_SYSTEM_TIMER 0x02
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#define PCI_SUBCLASS_SYSTEM_RTC 0x03
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#define PCI_SUBCLASS_SYSTEM_MISC 0x80
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/* 0x09 input subclasses */
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#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
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#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
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#define PCI_SUBCLASS_INPUT_MOUSE 0x02
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#define PCI_SUBCLASS_INPUT_MISC 0x80
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/* 0x0a dock subclasses */
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#define PCI_SUBCLASS_DOCK_GENERIC 0x00
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#define PCI_SUBCLASS_DOCK_MISC 0x80
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/* 0x0b processor subclasses */
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#define PCI_SUBCLASS_PROCESSOR_386 0x00
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#define PCI_SUBCLASS_PROCESSOR_486 0x01
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#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
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#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
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#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
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#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
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/* 0x0c serial bus subclasses */
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#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
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#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
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#define PCI_SUBCLASS_SERIALBUS_SSA 0x02
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#define PCI_SUBCLASS_SERIALBUS_USB 0x03
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#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04
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/*
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* PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
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*/
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#define PCI_BHLC_REG 0x0c
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#define PCI_BIST_SHIFT 24
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#define PCI_BIST_MASK 0xff
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#define PCI_BIST(bhlcr) \
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(((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
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#define PCI_HDRTYPE_SHIFT 16
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#define PCI_HDRTYPE_MASK 0xff
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#define PCI_HDRTYPE(bhlcr) \
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(((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
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#define PCI_HDRTYPE_TYPE(bhlcr) \
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(PCI_HDRTYPE(bhlcr) & 0x7f)
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#define PCI_HDRTYPE_MULTIFN(bhlcr) \
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((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
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#define PCI_LATTIMER_SHIFT 8
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#define PCI_LATTIMER_MASK 0xff
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#define PCI_LATTIMER(bhlcr) \
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(((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
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#define PCI_CACHELINE_SHIFT 0
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#define PCI_CACHELINE_MASK 0xff
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#define PCI_CACHELINE(bhlcr) \
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(((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
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/*
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* Mapping registers
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*/
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#define PCI_MAPREG_START 0x10
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#define PCI_MAPREG_END 0x28
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#define PCI_MAPREG_TYPE(mr) \
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((mr) & PCI_MAPREG_TYPE_MASK)
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#define PCI_MAPREG_TYPE_MASK 0x00000001
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#define PCI_MAPREG_TYPE_MEM 0x00000000
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#define PCI_MAPREG_TYPE_IO 0x00000001
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#define PCI_MAPREG_MEM_TYPE(mr) \
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((mr) & PCI_MAPREG_MEM_TYPE_MASK)
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#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
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#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
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#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
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#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
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#define PCI_MAPREG_MEM_CACHEABLE(mr) \
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(((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0)
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#define PCI_MAPREG_MEM_CACHEABLE_MASK 0x00000008
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#define PCI_MAPREG_MEM_ADDR(mr) \
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((mr) & PCI_MAPREG_MEM_ADDR_MASK)
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#define PCI_MAPREG_MEM_SIZE(mr) \
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(PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
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#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
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#define PCI_MAPREG_IO_ADDR(mr) \
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((mr) & PCI_MAPREG_IO_ADDR_MASK)
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#define PCI_MAPREG_IO_SIZE(mr) \
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(PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
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#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
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/*
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* Cardbus CIS pointer (PCI rev. 2.1)
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*/
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#define PCI_CARDBUS_CIS_REG 0x28
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/*
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* Subsystem identification register; contains a vendor ID and a device ID.
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* Types/macros for PCI_ID_REG apply.
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* (PCI rev. 2.1)
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*/
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#define PCI_SUBSYS_ID_REG 0x2c
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/*
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* capabilities link list (PCI rev. 2.2)
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*/
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#define PCI_CAPLISTPTR_REG 0x34
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#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
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#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
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#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
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#define PCI_CAP_PWRMGMT 1
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#define PCI_CAP_AGP 2
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#define PCI_CAP_VPD 3
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#define PCI_CAP_SLOTID 4
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#define PCI_CAP_MBI 5
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#define PCI_CAP_HOTSWAP 6
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/*
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* Interrupt Configuration Register; contains interrupt pin and line.
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*/
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#define PCI_INTERRUPT_REG 0x3c
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typedef u_int8_t pci_intr_pin_t;
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typedef u_int8_t pci_intr_line_t;
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#define PCI_INTERRUPT_PIN_SHIFT 8
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#define PCI_INTERRUPT_PIN_MASK 0xff
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#define PCI_INTERRUPT_PIN(icr) \
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(((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
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#define PCI_INTERRUPT_LINE_SHIFT 0
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#define PCI_INTERRUPT_LINE_MASK 0xff
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#define PCI_INTERRUPT_LINE(icr) \
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(((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
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#define PCI_INTERRUPT_PIN_NONE 0x00
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#define PCI_INTERRUPT_PIN_A 0x01
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#define PCI_INTERRUPT_PIN_B 0x02
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#define PCI_INTERRUPT_PIN_C 0x03
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#define PCI_INTERRUPT_PIN_D 0x04
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#endif /* _DEV_PCI_PCIREG_H_ */
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