619 lines
15 KiB
C
619 lines
15 KiB
C
/* $NetBSD: bpp.c,v 1.22 2004/03/17 17:04:58 pk Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: bpp.c,v 1.22 2004/03/17 17:04:58 pk Exp $");
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#include <sys/param.h>
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#include <sys/ioctl.h>
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#include <sys/fcntl.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/vnode.h>
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#include <sys/poll.h>
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#include <sys/select.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/signalvar.h>
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#include <sys/conf.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/autoconf.h>
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#include <dev/ic/lsi64854reg.h>
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#include <dev/ic/lsi64854var.h>
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#include <dev/sbus/sbusvar.h>
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#include <dev/sbus/bppreg.h>
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#define splbpp() spltty() /* XXX */
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#ifdef DEBUG
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#define DPRINTF(x) do { if (bppdebug) printf x ; } while (0)
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int bppdebug = 1;
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#else
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#define DPRINTF(x)
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#endif
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#if 0
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struct bpp_param {
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int bpp_dss; /* data setup to strobe */
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int bpp_dsw; /* data strobe width */
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int bpp_outputpins; /* Select/Autofeed/Init pins */
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int bpp_inputpins; /* Error/Select/Paperout pins */
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};
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#endif
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struct hwstate {
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u_int16_t hw_hcr; /* Hardware config register */
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u_int16_t hw_ocr; /* Operation config register */
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u_int8_t hw_tcr; /* Transfer Control register */
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u_int8_t hw_or; /* Output register */
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u_int16_t hw_irq; /* IRQ; polarity bits only */
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};
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struct bpp_softc {
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struct lsi64854_softc sc_lsi64854; /* base device */
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struct sbusdev sc_sd; /* sbus device */
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size_t sc_bufsz; /* temp buffer */
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caddr_t sc_buf;
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int sc_error; /* bottom-half error */
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int sc_flags;
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#define BPP_OPEN 0x01 /* Device is open */
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#define BPP_XCLUDE 0x02 /* Exclusive-open mode */
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#define BPP_ASYNC 0x04 /* Asynchronous I/O mode */
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#define BPP_LOCKED 0x08 /* DMA in progress */
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#define BPP_WANT 0x10 /* Waiting for DMA */
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struct selinfo sc_rsel;
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struct selinfo sc_wsel;
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struct proc *sc_asyncproc; /* Process to notify if async */
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/* Hardware state */
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struct hwstate sc_hwdefault;
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struct hwstate sc_hwcurrent;
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};
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static int bppmatch __P((struct device *, struct cfdata *, void *));
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static void bppattach __P((struct device *, struct device *, void *));
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static int bppintr __P((void *));
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static void bpp_setparams __P((struct bpp_softc *, struct hwstate *));
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CFATTACH_DECL(bpp, sizeof(struct bpp_softc),
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bppmatch, bppattach, NULL, NULL);
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extern struct cfdriver bpp_cd;
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dev_type_open(bppopen);
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dev_type_close(bppclose);
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dev_type_write(bppwrite);
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dev_type_ioctl(bppioctl);
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dev_type_poll(bpppoll);
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dev_type_kqfilter(bppkqfilter);
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const struct cdevsw bpp_cdevsw = {
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bppopen, bppclose, noread, bppwrite, bppioctl,
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nostop, notty, bpppoll, nommap, bppkqfilter,
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};
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#define BPPUNIT(dev) (minor(dev))
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int
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bppmatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct sbus_attach_args *sa = aux;
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return (strcmp("SUNW,bpp", sa->sa_name) == 0);
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}
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void
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bppattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct sbus_attach_args *sa = aux;
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struct bpp_softc *dsc = (void *)self;
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struct lsi64854_softc *sc = &dsc->sc_lsi64854;
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int burst, sbusburst;
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int node;
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sc->sc_bustag = sa->sa_bustag;
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sc->sc_dmatag = sa->sa_dmatag;
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node = sa->sa_node;
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/* Map device registers */
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot, sa->sa_offset, sa->sa_size,
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0, &sc->sc_regs) != 0) {
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printf("%s: cannot map registers\n", self->dv_xname);
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return;
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}
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/*
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* Get transfer burst size from PROM and plug it into the
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* controller registers. This is needed on the Sun4m; do
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* others need it too?
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*/
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sbusburst = ((struct sbus_softc *)parent)->sc_burst;
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if (sbusburst == 0)
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sbusburst = SBUS_BURST_32 - 1; /* 1->16 */
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burst = prom_getpropint(node, "burst-sizes", -1);
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if (burst == -1)
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/* take SBus burst sizes */
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burst = sbusburst;
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/* Clamp at parent's burst sizes */
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burst &= sbusburst;
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sc->sc_burst = (burst & SBUS_BURST_32) ? 32 :
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(burst & SBUS_BURST_16) ? 16 : 0;
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/* Join the Sbus device family */
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dsc->sc_sd.sd_reset = (void *)0;
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sbus_establish(&dsc->sc_sd, self);
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/* Initialize the DMA channel */
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sc->sc_channel = L64854_CHANNEL_PP;
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lsi64854_attach(sc);
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/* Establish interrupt handler */
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if (sa->sa_nintr) {
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sc->sc_intrchain = bppintr;
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sc->sc_intrchainarg = dsc;
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(void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY,
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bppintr, sc);
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}
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/* Allocate buffer XXX - should actually use dmamap_uio() */
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dsc->sc_bufsz = 1024;
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dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT);
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/* XXX read default state */
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{
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bus_space_handle_t h = sc->sc_regs;
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struct hwstate *hw = &dsc->sc_hwdefault;
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int ack_rate = sa->sa_frequency/1000000;
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hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR);
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hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR);
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hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR);
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hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR);
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DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n",
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hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or));
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/* Set these to sane values */
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hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK)
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| ((ack_rate<<BPP_HCR_DSW_SHFT)&BPP_HCR_DSW_MASK);
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hw->hw_ocr |= BPP_OCR_ACK_OP;
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}
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}
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void
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bpp_setparams(sc, hw)
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struct bpp_softc *sc;
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struct hwstate *hw;
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{
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u_int16_t irq;
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bus_space_tag_t t = sc->sc_lsi64854.sc_bustag;
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bus_space_handle_t h = sc->sc_lsi64854.sc_regs;
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bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr);
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bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr);
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bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr);
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bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or);
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/* Only change IRP settings in interrupt status register */
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irq = bus_space_read_2(t, h, L64854_REG_ICR);
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irq &= ~BPP_ALLIRP;
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irq |= (hw->hw_irq & BPP_ALLIRP);
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bus_space_write_2(t, h, L64854_REG_ICR, irq);
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DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n",
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hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq));
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}
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int
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bppopen(dev, flags, mode, p)
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dev_t dev;
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int flags, mode;
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struct proc *p;
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{
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int unit = BPPUNIT(dev);
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struct bpp_softc *sc;
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struct lsi64854_softc *lsi;
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u_int16_t irq;
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int s;
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if (unit >= bpp_cd.cd_ndevs)
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return (ENXIO);
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sc = bpp_cd.cd_devs[unit];
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if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE))
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return (EBUSY);
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lsi = &sc->sc_lsi64854;
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/* Set default parameters */
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sc->sc_hwcurrent = sc->sc_hwdefault;
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s = splbpp();
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bpp_setparams(sc, &sc->sc_hwdefault);
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splx(s);
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/* Enable interrupts */
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irq = BPP_ERR_IRQ_EN;
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irq |= sc->sc_hwdefault.hw_irq;
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bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq);
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return (0);
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}
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int
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bppclose(dev, flags, mode, p)
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dev_t dev;
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int flags, mode;
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struct proc *p;
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{
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struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)];
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struct lsi64854_softc *lsi = &sc->sc_lsi64854;
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u_int16_t irq;
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/* Turn off all interrupt enables */
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irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ;
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irq &= ~BPP_ALLEN;
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bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq);
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sc->sc_asyncproc = NULL;
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sc->sc_flags = 0;
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return (0);
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}
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int
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bppwrite(dev, uio, flags)
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dev_t dev;
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struct uio *uio;
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int flags;
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{
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struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)];
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struct lsi64854_softc *lsi = &sc->sc_lsi64854;
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int error = 0;
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int s;
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/*
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* Wait until the DMA engine is free.
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*/
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s = splbpp();
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while ((sc->sc_flags & BPP_LOCKED) != 0) {
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if ((flags & IO_NDELAY) != 0) {
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splx(s);
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return (EWOULDBLOCK);
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}
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sc->sc_flags |= BPP_WANT;
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error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0);
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if (error != 0) {
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splx(s);
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return (error);
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}
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}
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sc->sc_flags |= BPP_LOCKED;
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splx(s);
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/*
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* Move data from user space into our private buffer
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* and start DMA.
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*/
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while (uio->uio_resid > 0) {
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caddr_t bp = sc->sc_buf;
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size_t len = min(sc->sc_bufsz, uio->uio_resid);
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if ((error = uiomove(bp, len, uio)) != 0)
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break;
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while (len > 0) {
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u_int8_t tcr;
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size_t size = len;
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DMA_SETUP(lsi, &bp, &len, 0, &size);
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#ifdef DEBUG
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if (bppdebug) {
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int i;
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printf("bpp: writing %ld : ", len);
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for (i=0; i<len; i++) printf("%c(0x%x)", bp[i], bp[i]);
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printf("\n");
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}
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#endif
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/* Clear direction control bit */
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tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs,
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L64854_REG_TCR);
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tcr &= ~BPP_TCR_DIR;
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bus_space_write_1(lsi->sc_bustag, lsi->sc_regs,
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L64854_REG_TCR, tcr);
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/* Enable DMA */
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s = splbpp();
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DMA_GO(lsi);
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error = tsleep(sc, PZERO|PCATCH, "bppdma", 0);
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splx(s);
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if (error != 0)
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goto out;
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/* Bail out if bottom half reported an error */
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if ((error = sc->sc_error) != 0)
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goto out;
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/*
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* lsi64854_pp_intr() does this part.
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*
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* len -= size;
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*/
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}
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}
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out:
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DPRINTF(("bpp done %x\n", error));
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s = splbpp();
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sc->sc_flags &= ~BPP_LOCKED;
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if ((sc->sc_flags & BPP_WANT) != 0) {
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sc->sc_flags &= ~BPP_WANT;
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wakeup(sc->sc_buf);
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}
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splx(s);
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return (error);
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}
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/* move to header: */
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#define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate)
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#define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate)
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int
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bppioctl(dev, cmd, data, flag, p)
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dev_t dev;
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u_long cmd;
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caddr_t data;
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int flag;
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struct proc *p;
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{
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struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)];
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struct hwstate *hw, *chw;
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int error = 0;
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int s;
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switch(cmd) {
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case BPPIOCSPARAM:
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chw = &sc->sc_hwcurrent;
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hw = (struct hwstate *)data;
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/*
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* Extract and store user-settable bits.
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*/
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#define _bpp_set(reg,mask) do { \
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chw->reg &= ~(mask); \
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chw->reg |= (hw->reg & (mask)); \
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} while (0)
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_bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK);
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_bpp_set(hw_ocr, BPP_OCR_USER);
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_bpp_set(hw_tcr, BPP_TCR_USER);
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_bpp_set(hw_or, BPP_OR_USER);
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_bpp_set(hw_irq, BPP_IRQ_USER);
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#undef _bpp_set
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/* Apply settings */
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s = splbpp();
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bpp_setparams(sc, chw);
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splx(s);
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break;
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case BPPIOCGPARAM:
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*((struct hwstate *)data) = sc->sc_hwcurrent;
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break;
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case TIOCEXCL:
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s = splbpp();
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sc->sc_flags |= BPP_XCLUDE;
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splx(s);
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break;
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case TIOCNXCL:
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s = splbpp();
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sc->sc_flags &= ~BPP_XCLUDE;
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splx(s);
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break;
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case FIOASYNC:
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s = splbpp();
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if (*(int *)data) {
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if (sc->sc_asyncproc != NULL)
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error = EBUSY;
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else
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sc->sc_asyncproc = p;
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} else
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sc->sc_asyncproc = NULL;
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splx(s);
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break;
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default:
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break;
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}
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return (error);
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}
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int
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bpppoll(dev, events, p)
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dev_t dev;
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int events;
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struct proc *p;
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{
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struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)];
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int revents = 0;
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if (events & (POLLIN | POLLRDNORM)) {
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/* read is not yet implemented */
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}
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|
|
if (events & (POLLOUT | POLLWRNORM)) {
|
|
if ((sc->sc_flags & BPP_LOCKED) == 0)
|
|
revents |= (POLLOUT | POLLWRNORM);
|
|
}
|
|
|
|
if (revents == 0) {
|
|
if (events & (POLLIN | POLLRDNORM))
|
|
selrecord(p, &sc->sc_rsel);
|
|
if (events & (POLLOUT | POLLWRNORM))
|
|
selrecord(p, &sc->sc_wsel);
|
|
}
|
|
|
|
return (revents);
|
|
}
|
|
|
|
static void
|
|
filt_bpprdetach(struct knote *kn)
|
|
{
|
|
struct bpp_softc *sc = kn->kn_hook;
|
|
int s;
|
|
|
|
s = splbpp();
|
|
SLIST_REMOVE(&sc->sc_rsel.sel_klist, kn, knote, kn_selnext);
|
|
splx(s);
|
|
}
|
|
|
|
static int
|
|
filt_bppread(struct knote *kn, long hint)
|
|
{
|
|
/* XXX Read not yet implemented. */
|
|
return (0);
|
|
}
|
|
|
|
static const struct filterops bppread_filtops =
|
|
{ 1, NULL, filt_bpprdetach, filt_bppread };
|
|
|
|
static void
|
|
filt_bppwdetach(struct knote *kn)
|
|
{
|
|
struct bpp_softc *sc = kn->kn_hook;
|
|
int s;
|
|
|
|
s = splbpp();
|
|
SLIST_REMOVE(&sc->sc_wsel.sel_klist, kn, knote, kn_selnext);
|
|
splx(s);
|
|
}
|
|
|
|
static int
|
|
filt_bpfwrite(struct knote *kn, long hint)
|
|
{
|
|
struct bpp_softc *sc = kn->kn_hook;
|
|
|
|
if (sc->sc_flags & BPP_LOCKED)
|
|
return (0);
|
|
|
|
kn->kn_data = 0; /* XXXLUKEM (thorpej): what to put here? */
|
|
return (1);
|
|
}
|
|
|
|
static const struct filterops bppwrite_filtops =
|
|
{ 1, NULL, filt_bppwdetach, filt_bpfwrite };
|
|
|
|
int
|
|
bppkqfilter(dev_t dev, struct knote *kn)
|
|
{
|
|
struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)];
|
|
struct klist *klist;
|
|
int s;
|
|
|
|
switch (kn->kn_filter) {
|
|
case EVFILT_READ:
|
|
klist = &sc->sc_rsel.sel_klist;
|
|
kn->kn_fop = &bppread_filtops;
|
|
break;
|
|
|
|
case EVFILT_WRITE:
|
|
klist = &sc->sc_wsel.sel_klist;
|
|
kn->kn_fop = &bppwrite_filtops;
|
|
break;
|
|
|
|
default:
|
|
return (1);
|
|
}
|
|
|
|
kn->kn_hook = sc;
|
|
|
|
s = splbpp();
|
|
SLIST_INSERT_HEAD(klist, kn, kn_selnext);
|
|
splx(s);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
bppintr(arg)
|
|
void *arg;
|
|
{
|
|
struct bpp_softc *sc = arg;
|
|
struct lsi64854_softc *lsi = &sc->sc_lsi64854;
|
|
u_int16_t irq;
|
|
|
|
/* First handle any possible DMA interrupts */
|
|
if (lsi64854_pp_intr((void *)lsi) == -1)
|
|
sc->sc_error = 1;
|
|
|
|
irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR);
|
|
/* Ack all interrupts */
|
|
bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR,
|
|
irq | BPP_ALLIRQ);
|
|
|
|
DPRINTF(("bpp_intr: %x\n", irq));
|
|
/* Did our device interrupt? */
|
|
if ((irq & BPP_ALLIRQ) == 0)
|
|
return (0);
|
|
|
|
if ((sc->sc_flags & BPP_LOCKED) != 0)
|
|
wakeup(sc);
|
|
else if ((sc->sc_flags & BPP_WANT) != 0) {
|
|
sc->sc_flags &= ~BPP_WANT;
|
|
wakeup(sc->sc_buf);
|
|
} else {
|
|
selnotify(&sc->sc_wsel, 0);
|
|
if (sc->sc_asyncproc != NULL)
|
|
psignal(sc->sc_asyncproc, SIGIO);
|
|
}
|
|
return (1);
|
|
}
|