672 lines
17 KiB
C
672 lines
17 KiB
C
/* $NetBSD: pci_intr_fixup.c,v 1.6 2000/07/09 00:42:47 mycroft Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* PCI Interrupt Router support.
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*/
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#include "opt_pcibios.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <i386/isa/icu.h>
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#include <i386/pci/pci_intr_fixup.h>
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#include <i386/pci/pcibios.h>
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struct pciintr_link_map {
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int link;
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int clink;
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int irq;
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u_int16_t bitmap;
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int fixup_stage;
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int old_irq;
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SIMPLEQ_ENTRY(pciintr_link_map) list;
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};
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pciintr_icu_tag_t pciintr_icu_tag;
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pciintr_icu_handle_t pciintr_icu_handle;
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struct pciintr_link_map *pciintr_link_lookup_pin
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__P((struct pcibios_intr_routing *, int));
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struct pciintr_link_map *pciintr_link_lookup_link __P((int));
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struct pciintr_link_map *pciintr_link_alloc __P((struct pcibios_intr_routing *,
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int));
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struct pcibios_intr_routing *pciintr_pir_lookup __P((int, int));
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int pciintr_link_init __P((void));
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int pciintr_link_fixup __P((void));
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int pciintr_link_route __P((u_int16_t *));
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int pciintr_irq_release __P((u_int16_t *));
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int pciintr_header_fixup __P((pci_chipset_tag_t));
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void pciintr_do_header_fixup __P((pci_chipset_tag_t, pcitag_t));
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SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list;
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const struct pciintr_icu_table {
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pci_vendor_id_t piit_vendor;
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pci_product_id_t piit_product;
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int (*piit_init) __P((pci_chipset_tag_t,
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bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *,
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pciintr_icu_handle_t *));
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} pciintr_icu_table[] = {
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX,
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piix_init },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA,
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piix_init },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA,
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piix_init },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA,
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piix_init },
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{ PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558,
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opti82c558_init },
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{ PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700,
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opti82c700_init },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA,
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via82c586_init, },
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{ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503,
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sis85c503_init },
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{ 0, 0,
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NULL },
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};
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const struct pciintr_icu_table *pciintr_icu_lookup __P((pcireg_t));
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const struct pciintr_icu_table *
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pciintr_icu_lookup(id)
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pcireg_t id;
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{
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const struct pciintr_icu_table *piit;
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for (piit = pciintr_icu_table;
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piit->piit_init != NULL;
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piit++) {
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if (PCI_VENDOR(id) == piit->piit_vendor &&
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PCI_PRODUCT(id) == piit->piit_product)
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return (piit);
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}
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return (NULL);
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}
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struct pciintr_link_map *
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pciintr_link_lookup_pin(pir, pin)
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struct pcibios_intr_routing *pir;
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int pin;
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{
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return (pciintr_link_lookup_link(pir->linkmap[pin].link));
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}
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struct pciintr_link_map *
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pciintr_link_lookup_link(link)
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int link;
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{
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struct pciintr_link_map *l;
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for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL;
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l = SIMPLEQ_NEXT(l, list)) {
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if (l->link == link)
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return (l);
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}
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return (NULL);
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}
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struct pciintr_link_map *
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pciintr_link_alloc(pir, pin)
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struct pcibios_intr_routing *pir;
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int pin;
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{
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struct pciintr_link_map *l, *lstart;
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l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT);
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if (l == NULL)
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panic("pciintr_link_alloc");
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memset(l, 0, sizeof(*l));
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l->link = pir->linkmap[pin].link;
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l->bitmap = pir->linkmap[pin].bitmap;
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lstart = SIMPLEQ_FIRST(&pciintr_link_map_list);
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if (lstart == NULL || lstart->link < l->link)
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SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list);
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else
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SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list);
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return (l);
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}
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struct pcibios_intr_routing *
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pciintr_pir_lookup(bus, device)
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int bus, device;
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{
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struct pcibios_intr_routing *pir;
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int entry;
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if (pcibios_pir_table == NULL)
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return (NULL);
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for (entry = 0; entry < pcibios_pir_table_nentries; entry++) {
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pir = &pcibios_pir_table[entry];
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if (pir->bus == bus && ((pir->device >> 3) & 0x1f) == device)
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return (pir);
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}
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return (NULL);
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}
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int
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pciintr_link_init()
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{
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int entry, pin, error, link, clink;
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struct pcibios_intr_routing *pir;
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struct pciintr_link_map *l;
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if (pcibios_pir_table == NULL) {
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/* No PIR table; can't do anything. */
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printf("pciintr_link_init: no PIR table\n");
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return (1);
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}
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error = 0;
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SIMPLEQ_INIT(&pciintr_link_map_list);
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for (entry = 0; entry < pcibios_pir_table_nentries; entry++) {
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pir = &pcibios_pir_table[entry];
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for (pin = 0; pin < 4; pin++) {
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link = pir->linkmap[pin].link;
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if (link == 0) {
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/* No connection for this pin. */
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continue;
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}
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/*
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* Check the link value by asking the ICU for
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* the canonical link value.
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*/
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if (pciintr_icu_getclink(pciintr_icu_tag,
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pciintr_icu_handle, link, &clink) != 0) {
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/*
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* Table entry is bogus. Just ignore it.
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*/
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#ifdef PCIINTR_DEBUG
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printf("pciintr_link_init: bad table entry: "
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"bus %d device %d link 0x%02x\n",
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pir->bus, (pir->device >> 3 & 0x1f), link);
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#endif
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continue;
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}
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/*
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* Multiple devices may be wired to the same
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* interrupt; check to see if we've seen this
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* one already. If not, allocate a new link
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* map entry and stuff it in the map.
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*/
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l = pciintr_link_lookup_pin(pir, pin);
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if (l == NULL)
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(void) pciintr_link_alloc(pir, pin);
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}
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}
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return (error);
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}
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int
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pciintr_link_fixup()
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{
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struct pciintr_link_map *l;
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u_int16_t pciirq, bitmap;
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int i, j, cnt, irq;
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/*
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* First stage: Attempt to connect PIRQs which aren't
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* yet connected.
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*/
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pciirq = 0;
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for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL;
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l = SIMPLEQ_NEXT(l, list)) {
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/*
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* Get the canonical link value for this entry.
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*/
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if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle,
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l->link, &l->clink) != 0) {
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/*
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* ICU doesn't understand this link value.
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*/
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#ifdef PCIINTR_DEBUG
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printf("pciintr_link_fixup: link 0x%02x invalid\n",
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l->link);
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#endif
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l->clink = -1;
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continue;
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}
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/*
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* Determine if this PIRQ is mapped to an IRQ.
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*/
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if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle,
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l->clink, &irq) != 0) {
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/*
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* ICU doesn't understand this PIRQ value.
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*/
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l->clink = -1;
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#ifdef PCIINTR_DEBUG
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printf("pciintr_link_fixup: PIRQ %d invalid\n",
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l->clink);
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#endif
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continue;
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}
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if (irq == 0xff) {
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/*
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* Interrupt isn't connected. Attempt to assign
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* it to an IRQ.
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*/
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#ifdef PCIINTR_DEBUG
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printf("pciintr_link_fixup: PIRQ %d not connected",
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l->clink);
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#endif
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bitmap = l->bitmap;
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for (i = 0, j = 0xff, cnt = 0; i < 16; i++)
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if (bitmap & (1 << i))
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j = i, cnt++;
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/*
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* Just do the easy case now; we'll defer the
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* harder ones to Stage 2.
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*/
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if (cnt == 1) {
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l->irq = j;
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l->old_irq = irq;
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l->fixup_stage = 1;
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pciirq |= 1 << j;
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#ifdef PCIINTR_DEBUG
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printf(", assigning IRQ %d", l->irq);
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#endif
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}
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#ifdef PCIINTR_DEBUG
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printf("\n");
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#endif
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} else {
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/*
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* Interrupt is already connected. Don't do
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* anything to it.
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*/
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l->irq = irq;
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pciirq |= 1 << irq;
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#ifdef PCIINTR_DEBUG
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printf("pciintr_link_fixup: PIRQ %d already connected "
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"to IRQ %d\n", l->clink, l->irq);
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#endif
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}
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}
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/*
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* Stage 2: Attempt to connect PIRQs which we didn't
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* connect in Stage 1.
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*/
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for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL;
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l = SIMPLEQ_NEXT(l, list)) {
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if (l->irq != 0)
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continue;
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bitmap = l->bitmap;
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for (i = 0; i < 16; i++) {
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if ((pciirq & (1 << i)) != 0 &&
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(bitmap & (1 << i)) != 0) {
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/*
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* This IRQ is a valid PCI IRQ already
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* connected to another PIRQ, and also an
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* IRQ our PIRQ can use; connect it up!
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*/
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l->irq = i;
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l->old_irq = 0xff;
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l->fixup_stage = 2;
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#ifdef PCIINTR_DEBUG
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printf("pciintr_link_fixup: assigning "
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"IRQ %d to PIRQ %d\n", l->irq,
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l->clink);
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#endif
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break;
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}
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}
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}
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#ifdef PCIBIOS_IRQS_HINT
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/*
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* Stage 3: The worst case. I need configuration hint that
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* user supplied a mask for the PCI irqs
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*/
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pciirq = PCIBIOS_IRQS_HINT;
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for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL;
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l = SIMPLEQ_NEXT(l, list)) {
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if (l->irq != 0)
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continue;
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for (i = 0; i < 16; i++) {
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if ((pciirq & (1 << i)) != 0 &&
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(bitmap & (1 << i)) != 0) {
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l->irq = i;
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l->old_irq = 0xff;
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l->fixup_stage = 3;
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#ifdef PCIINTR_DEBUG
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printf("pciintr_link_fixup (stage 3): "
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"assigning IRQ %d to PIRQ %d\n",
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l->irq, l->clink);
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#endif
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break;
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}
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}
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}
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#endif /* PCIBIOS_IRQS_HINT */
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return (0);
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}
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int
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pciintr_link_route(pciirq)
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u_int16_t *pciirq;
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{
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struct pciintr_link_map *l;
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int rv = 0;
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*pciirq = 0;
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for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL;
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l = SIMPLEQ_NEXT(l, list)) {
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if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle,
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l->clink, l->irq) != 0 ||
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pciintr_icu_set_trigger(pciintr_icu_tag, pciintr_icu_handle,
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l->irq, IST_LEVEL) != 0) {
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printf("pciintr_link_route: route of PIRQ %d -> IRQ %d"
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" failed\n", l->clink, l->irq);
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rv = 1;
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} else {
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/*
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* Succssfully routed interrupt. Mark this as
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* a PCI interrupt.
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*/
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*pciirq |= (1 << l->irq);
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}
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}
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return (rv);
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}
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int
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pciintr_irq_release(pciirq)
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u_int16_t *pciirq;
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{
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int i;
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for (i = 0; i < 16; i++) {
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if ((*pciirq & (1 << i)) == 0)
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(void) pciintr_icu_set_trigger(pciintr_icu_tag,
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pciintr_icu_handle, i, IST_EDGE);
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}
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return (0);
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}
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int
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pciintr_header_fixup(pc)
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pci_chipset_tag_t pc;
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{
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#ifdef PCIBIOSVERBOSE
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printf("--------------------------------------------\n");
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printf(" device vendor product pin PIRQ IRQ stage\n");
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printf("--------------------------------------------\n");
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#endif
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pci_device_foreach(pc, pcibios_max_bus, pciintr_do_header_fixup);
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#ifdef PCIBIOSVERBOSE
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printf("--------------------------------------------\n");
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#endif
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return (0);
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}
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void
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pciintr_do_header_fixup(pc, tag)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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{
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struct pcibios_intr_routing *pir;
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struct pciintr_link_map *l;
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int pin, irq, link;
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int bus, device, function;
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pcireg_t intr, id;
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pci_decompose_tag(pc, tag, &bus, &device, &function);
|
|
id = pci_conf_read(pc, tag, PCI_ID_REG);
|
|
|
|
intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
|
|
pin = PCI_INTERRUPT_PIN(intr);
|
|
irq = PCI_INTERRUPT_LINE(intr);
|
|
|
|
if (pin == 0) {
|
|
/*
|
|
* No interrupt used.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
pir = pciintr_pir_lookup(bus, device);
|
|
if (pir == NULL || (link = pir->linkmap[pin - 1].link) == 0) {
|
|
/*
|
|
* Interrupt not connected; no
|
|
* need to change.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
l = pciintr_link_lookup_link(link);
|
|
if (l == NULL) {
|
|
/*
|
|
* No link map entry?!
|
|
*/
|
|
printf("pciintr_header_fixup: no entry for link 0x%02x "
|
|
"(%d:%d:%d:%c)\n", link, bus, device, function,
|
|
'@' + pin);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck
|
|
* with them.
|
|
*/
|
|
if (irq == 14 || irq == 15)
|
|
return;
|
|
|
|
#ifdef PCIBIOSVERBOSE
|
|
printf("%03d:%02d:%d 0x%04x 0x%04x %c 0x%02x %02d %d\n",
|
|
bus, device, function, PCI_VENDOR(id), PCI_PRODUCT(id),
|
|
'@' + pin, l->clink, l->irq, l->fixup_stage);
|
|
#endif
|
|
|
|
intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
|
|
intr |= (l->irq << PCI_INTERRUPT_LINE_SHIFT);
|
|
pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
|
|
}
|
|
|
|
int
|
|
pci_intr_fixup(pc, iot, pciirq)
|
|
pci_chipset_tag_t pc;
|
|
bus_space_tag_t iot;
|
|
u_int16_t *pciirq;
|
|
{
|
|
const struct pciintr_icu_table *piit = NULL;
|
|
pcitag_t icutag;
|
|
pcireg_t icuid;
|
|
|
|
/*
|
|
* Attempt to initialize our PCI interrupt router. If
|
|
* the PIR Table is present in ROM, use the location
|
|
* specified by the PIR Table, and use the compat ID,
|
|
* if present. Otherwise, we have to look for the router
|
|
* ourselves (the PCI-ISA bridge).
|
|
*/
|
|
if (pcibios_pir_header.signature != 0) {
|
|
icutag = pci_make_tag(pc, pcibios_pir_header.router_bus,
|
|
(pcibios_pir_header.router_devfunc >> 3) & 0x1f,
|
|
pcibios_pir_header.router_devfunc & 7);
|
|
icuid = pcibios_pir_header.compat_router;
|
|
if (icuid == 0 ||
|
|
(piit = pciintr_icu_lookup(icuid)) == NULL) {
|
|
/*
|
|
* No compat ID, or don't know the compat ID? Read
|
|
* it from the configuration header.
|
|
*/
|
|
icuid = pci_conf_read(pc, icutag, PCI_ID_REG);
|
|
}
|
|
if (piit == NULL)
|
|
piit = pciintr_icu_lookup(icuid);
|
|
} else {
|
|
int device, maxdevs = pci_bus_maxdevs(pc, 0);
|
|
|
|
/*
|
|
* Search configuration space for a known interrupt
|
|
* router.
|
|
*/
|
|
for (device = 0; device < maxdevs; device++) {
|
|
icutag = pci_make_tag(pc, 0, device, 0);
|
|
icuid = pci_conf_read(pc, icutag, PCI_ID_REG);
|
|
|
|
/* Invalid vendor ID value? */
|
|
if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID)
|
|
continue;
|
|
/* XXX Not invalid, but we've done this ~forever. */
|
|
if (PCI_VENDOR(icuid) == 0)
|
|
continue;
|
|
|
|
piit = pciintr_icu_lookup(icuid);
|
|
if (piit != NULL)
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (piit == NULL) {
|
|
printf("pci_intr_fixup: no compatible PCI ICU found\n");
|
|
return (-1); /* non-fatal */
|
|
}
|
|
|
|
/*
|
|
* Initialize the PCI ICU.
|
|
*/
|
|
if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag,
|
|
&pciintr_icu_handle) != 0)
|
|
return (-1); /* non-fatal */
|
|
|
|
/*
|
|
* Initialize the PCI interrupt link map.
|
|
*/
|
|
if (pciintr_link_init())
|
|
return (-1); /* non-fatal */
|
|
|
|
/*
|
|
* Fix up the link->IRQ mappings.
|
|
*/
|
|
if (pciintr_link_fixup() != 0)
|
|
return (-1); /* non-fatal */
|
|
|
|
/*
|
|
* Now actually program the PCI ICU with the new
|
|
* routing information.
|
|
*/
|
|
if (pciintr_link_route(pciirq) != 0)
|
|
return (1); /* fatal */
|
|
|
|
/*
|
|
* Now that we've routed all of the PIRQs, rewrite the PCI
|
|
* configuration headers to reflect the new mapping.
|
|
*/
|
|
if (pciintr_header_fixup(pc) != 0)
|
|
return (1); /* fatal */
|
|
|
|
/*
|
|
* Free any unused PCI IRQs for ISA devices.
|
|
*/
|
|
if (pciintr_irq_release(pciirq) != 0)
|
|
return (-1); /* non-fatal */
|
|
|
|
/*
|
|
* All done!
|
|
*/
|
|
return (0); /* success! */
|
|
}
|