264 lines
7.9 KiB
ArmAsm
264 lines
7.9 KiB
ArmAsm
/* $NetBSD: marvell_start.S,v 1.8 2014/08/30 13:28:07 kiyohara Exp $ */
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/*
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* Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
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* All rights reserved.
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*
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* Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM
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* Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the project nor the name of SOUM Corporation
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec Corporation may not be used to endorse or
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* promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_cputypes.h"
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#include "opt_mvsoc.h"
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#include <evbarm/marvell/marvellreg.h>
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#include "assym.h"
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RCSID("$NetBSD: marvell_start.S,v 1.8 2014/08/30 13:28:07 kiyohara Exp $")
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#ifndef SDRAM_START
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#define SDRAM_START 0x00000000
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#endif
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#define SHEEVA 1
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#define PJ4B 2
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/*
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* CPWAIT -- Canonical method to wait for CP15 update.
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* NOTE: Clobbers the specified temp reg.
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* copied from arm/arm/cpufunc_asm_xscale.S
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* XXX: better be in a common header file.
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*/
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#define CPWAIT_BRANCH \
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sub pc, pc, #4
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#define CPWAIT(tmp) \
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mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
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mov tmp, tmp /* wait for it to complete */ ;\
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CPWAIT_BRANCH /* branch to next insn */
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/*
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* Kernel start routine for Marvell boards
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* this code is excuted at the very first after the kernel is loaded
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* by U-Boot.
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*/
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.text
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.global _C_LABEL(marvell_start)
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_C_LABEL(marvell_start):
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/* The Loader for Marvell board is u-boot. it's running on RAM */
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/*
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* Kernel is loaded in SDRAM (0x00200000..), and is expected to run
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* in VA 0xc0200000..
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*/
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/* Check cores */
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mrc p15, 0, r4, c0, c0, 0
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and r4, r4, #CPU_ID_CPU_MASK
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adr r5, cores_start
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adr r6, cores_end
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0:
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cmp r5, r6
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beq 1f
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ldmia r5!, {r7, r8}
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cmp r4, r7
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bne 0b
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cmp r8, #SHEEVA
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bne 1f
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sheeva_l2_disable:
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/* Make sure L2 is disabled */
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mrc p15, 1, r5, c15, c1, 0 @ Get Marvell Extra Features Register
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bic r5, r5, #0x00400000 @ disable L2 cache
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mcr p15, 1, r5, c15, c1, 0
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#ifdef SHEEVA_L2_CACHE_WT
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/* L2 WT Mode */
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ldr r5, =0xf1020128 /* CPU L2 Configuration Register */
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ldr r6, [r5]
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bic r6, r6, #0x10 /* Force Write Through */
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str r6, [r5]
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#endif
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1:
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/* save u-boot's args */
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adr r4, u_boot_args
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nop
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nop
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nop
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stmia r4!, {r0, r1, r2, r3}
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nop
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nop
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nop
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#if defined(MVSOC_FIXUP_DEVID) && MVSOC_FIXUP_DEVID > 0
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adr r6, marvell_interregs_pbase
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ldr r7, [r6]
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add r7, r7, #0x40000
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ldr r6, [r7]
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bic r6, r6, 0xff000000
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bic r6, r6, 0x00ff0000
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/*
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* Some SoC returns ugly DeviceID. Fixup it.
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*/
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adr r5, devid
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ldr r5, [r5]
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orr r6, r6, r5, lsl #16
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str r6, [r7]
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b 1f
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devid:
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.word MVSOC_FIXUP_DEVID
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marvell_interregs_pbase:
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.word MARVELL_INTERREGS_PBASE
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#endif
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1:
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/* build page table from scratch */
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ldr r0, Lstartup_pagetable /* pagetable */
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adr r4, mmu_init_table
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b 3f
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2:
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str r3, [r0, r2]
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add r2, r2, #4
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add r3, r3, #(L1_S_SIZE)
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adds r1, r1, #-1
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bhi 2b
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3:
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ldmia r4!, {r1, r2, r3} /* # of sections, VA, PA|attr */
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cmp r1, #0
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bne 2b
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mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
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mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
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cmp r8, #PJ4B
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mcreq p15, 0, r0, c2, c0, 1 /* Set TTB1 */
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moveq r1, #TTBCR_S_N_1
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mcreq p15, 0, r1, c2, c0, 2 /* Set TTBCR */
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mov r0, #0
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mcreq p15, 0, r0, c8, c7, 0 /* Flush TLB */
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mcreq p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
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mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */
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mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */
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/* Ensure safe Translation Table. */
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/* Set the Domain Access register. Very important! */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0
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/* Enable MMU */
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mrc p15, 0, r0, c1, c0, 0
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cmp r8, #PJ4B
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orreq r0, r0, #CPU_CONTROL_XP_ENABLE
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biceq r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE)
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biceq r0, r0, #(CPU_CONTROL_IC_ENABLE)
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biceq r0, r0, #(CPU_CONTROL_BPRD_ENABLE)
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orr r0, r0, #CPU_CONTROL_SYST_ENABLE
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orr r0, r0, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT(r0)
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/* Jump to kernel code in TRUE VA */
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adr r0, Lstart
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ldr pc, [r0]
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Lstart:
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.word start
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#ifndef STARTUP_PAGETABLE_ADDR
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#define STARTUP_PAGETABLE_ADDR 0x00004000 /* aligned 16kByte */
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#endif
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Lstartup_pagetable:
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.word STARTUP_PAGETABLE_ADDR
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.globl _C_LABEL(u_boot_args)
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u_boot_args:
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.space 16 /* r0, r1, r2, r3 */
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cores_start:
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.word CPU_ID_MV88SV131, SHEEVA
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.word CPU_ID_MV88FR571_VD, SHEEVA /* Is it Sheeva? */
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.word CPU_ID_MV88SV581X_V6, PJ4B
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.word CPU_ID_MV88SV581X_V7, PJ4B
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.word CPU_ID_MV88SV584X_V7, PJ4B
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.word CPU_ID_ARM_88SV581X_V6, PJ4B
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.word CPU_ID_ARM_88SV581X_V7, PJ4B
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.word 0, 0
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cores_end:
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word n_sec ; \
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.word 4 * ((va) >> L1_S_SHIFT) ; \
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.word (pa) | (attr) ;
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mmu_init_table:
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/* fill all table VA==PA */
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MMU_INIT(0x00000000, 0x00000000,
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1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP_KRW)
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/* map SDRAM VA==PA, WT cacheable */
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MMU_INIT(SDRAM_START, SDRAM_START,
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128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW)
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/* map VA KERNEL_BASE_EXT..KERNEL_BASE_EXT+7ffffff to PA 0x00000000..0x07ffffff */
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MMU_INIT(KERNEL_BASE_EXT, SDRAM_START,
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128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW)
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.word 0 /* end of table */
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