624 lines
17 KiB
C
624 lines
17 KiB
C
/* $NetBSD: cs4231_sbus.c,v 1.53 2022/07/21 14:41:59 andvar Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2002, 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cs4231_sbus.c,v 1.53 2022/07/21 14:41:59 andvar Exp $");
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#include "audio.h"
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#if NAUDIO > 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <dev/sbus/sbusvar.h>
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#include <sys/audioio.h>
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#include <dev/audio/audio_if.h>
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#include <dev/ic/ad1848reg.h>
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#include <dev/ic/cs4231reg.h>
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#include <dev/ic/ad1848var.h>
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#include <dev/ic/cs4231var.h>
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#include <dev/ic/apcdmareg.h>
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#ifdef AUDIO_DEBUG
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int cs4231_sbus_debug = 0;
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#define DPRINTF(x) if (cs4231_sbus_debug) printf x
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#else
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#define DPRINTF(x)
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#endif
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/* where APC DMA registers are located */
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#define CS4231_APCDMA_OFFSET 16
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/* interrupt enable bits except those specific for playback/capture */
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#define APC_ENABLE (APC_EI | APC_IE | APC_EIE)
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struct cs4231_sbus_softc {
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struct cs4231_softc sc_cs4231;
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void *sc_pint;
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void *sc_rint;
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bus_space_tag_t sc_bt; /* DMA controller tag */
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bus_space_handle_t sc_bh; /* DMA controller registers */
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};
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static int cs4231_sbus_match(device_t, cfdata_t, void *);
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static void cs4231_sbus_attach(device_t, device_t, void *);
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static int cs4231_sbus_pint(void *);
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static int cs4231_sbus_rint(void *);
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CFATTACH_DECL_NEW(audiocs_sbus, sizeof(struct cs4231_sbus_softc),
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cs4231_sbus_match, cs4231_sbus_attach, NULL, NULL);
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/* audio_hw_if methods specific to apc DMA */
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static int cs4231_sbus_trigger_output(void *, void *, void *, int,
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void (*)(void *), void *,
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const audio_params_t *);
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static int cs4231_sbus_trigger_input(void *, void *, void *, int,
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void (*)(void *), void *,
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const audio_params_t *);
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static int cs4231_sbus_halt_output(void *);
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static int cs4231_sbus_halt_input(void *);
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const struct audio_hw_if audiocs_sbus_hw_if = {
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.open = cs4231_open,
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.close = cs4231_close,
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.query_format = ad1848_query_format,
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.set_format = ad1848_set_format,
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.commit_settings = ad1848_commit_settings,
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.halt_output = cs4231_sbus_halt_output,
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.halt_input = cs4231_sbus_halt_input,
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.getdev = cs4231_getdev,
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.set_port = cs4231_set_port,
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.get_port = cs4231_get_port,
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.query_devinfo = cs4231_query_devinfo,
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.allocm = cs4231_malloc,
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.freem = cs4231_free,
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.get_props = cs4231_get_props,
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.trigger_output = cs4231_sbus_trigger_output,
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.trigger_input = cs4231_sbus_trigger_input,
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.get_locks = ad1848_get_locks,
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};
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#ifdef AUDIO_DEBUG
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static void cs4231_sbus_regdump(const char *, struct cs4231_sbus_softc *);
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#endif
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static int cs4231_sbus_intr(void *);
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static int
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cs4231_sbus_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct sbus_attach_args *sa;
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sa = aux;
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return strcmp(sa->sa_name, AUDIOCS_PROM_NAME) == 0;
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}
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static void
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cs4231_sbus_attach(device_t parent, device_t self, void *aux)
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{
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struct cs4231_sbus_softc *sbsc;
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struct cs4231_softc *sc;
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struct sbus_attach_args *sa;
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bus_space_handle_t bh;
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sbsc = device_private(self);
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sc = &sbsc->sc_cs4231;
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sa = aux;
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sbsc->sc_bt = sc->sc_bustag = sa->sa_bustag;
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sc->sc_dmatag = sa->sa_dmatag;
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sbsc->sc_pint = sparc_softintr_establish(IPL_SCHED,
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(void *)cs4231_sbus_pint, sc);
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sbsc->sc_rint = sparc_softintr_establish(IPL_SCHED,
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(void *)cs4231_sbus_rint, sc);
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/*
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* Map my registers in, if they aren't already in virtual
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* address space.
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*/
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if (sa->sa_npromvaddrs) {
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sbus_promaddr_to_handle(sa->sa_bustag,
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sa->sa_promvaddrs[0], &bh);
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} else {
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if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
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sa->sa_offset, sa->sa_size, 0, &bh) != 0) {
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aprint_error("%s @ sbus: cannot map registers\n",
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device_xname(self));
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return;
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}
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}
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bus_space_subregion(sa->sa_bustag, bh, CS4231_APCDMA_OFFSET,
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APC_DMA_SIZE, &sbsc->sc_bh);
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cs4231_common_attach(sc, self, bh);
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printf("\n");
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ad1848_init_locks(&sc->sc_ad1848, IPL_SCHED);
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/* Establish interrupt channel */
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if (sa->sa_nintr)
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bus_intr_establish(sa->sa_bustag,
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sa->sa_pri, IPL_SCHED,
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cs4231_sbus_intr, sbsc);
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audio_attach_mi(&audiocs_sbus_hw_if, sbsc, self);
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}
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#ifdef AUDIO_DEBUG
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static void
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cs4231_sbus_regdump(const char *label, struct cs4231_sbus_softc *sc)
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{
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char bits[128];
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printf("cs4231regdump(%s): regs:", label);
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printf("dmapva: 0x%x; ",
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_PVA));
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printf("dmapc: 0x%x; ",
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_PC));
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printf("dmapnva: 0x%x; ",
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_PNVA));
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printf("dmapnc: 0x%x\n",
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_PNC));
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printf("dmacva: 0x%x; ",
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_CVA));
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printf("dmacc: 0x%x; ",
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_CC));
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printf("dmacnva: 0x%x; ",
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_CNVA));
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printf("dmacnc: 0x%x\n",
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_CNC));
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snprintb(bits, sizeof(bits), APC_BITS,
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bus_space_read_4(sc->sc_bt, sc->sc_bh, APC_DMA_CSR));
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printf("apc_dmacsr=%s\n", bits);
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ad1848_dump_regs(&sc->sc_cs4231.sc_ad1848);
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}
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#endif /* AUDIO_DEBUG */
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static int
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cs4231_sbus_trigger_output(void *addr, void *start, void *end, int blksize,
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void (*intr)(void *), void *arg,
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const audio_params_t *param)
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{
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struct cs4231_sbus_softc *sbsc;
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struct cs4231_softc *sc;
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struct cs_transfer *t;
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uint32_t csr;
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bus_addr_t dmaaddr;
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bus_size_t dmasize;
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int ret;
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#ifdef AUDIO_DEBUG
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char bits[128];
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#endif
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sbsc = addr;
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sc = &sbsc->sc_cs4231;
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t = &sc->sc_playback;
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ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
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start, end, blksize, intr, arg);
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if (ret != 0)
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return ret;
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DPRINTF(("trigger_output: was: %x %d, %x %d\n",
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PC),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNC)));
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/* load first block */
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNVA, dmaaddr);
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNC, dmasize);
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DPRINTF(("trigger_output: 1st: %x %d, %x %d\n",
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PC),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNC)));
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csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
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#ifdef AUDIO_DEBUG
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snprintb(bits, sizeof(bits), APC_BITS, csr);
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#endif
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DPRINTF(("trigger_output: csr=%s\n", bits));
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if ((csr & PDMA_GO) == 0 || (csr & APC_PPAUSE) != 0) {
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int cfg;
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csr &= ~(APC_PPAUSE | APC_PMIE | APC_INTR_MASK);
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
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csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
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csr &= ~APC_INTR_MASK;
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csr |= APC_ENABLE | APC_PIE | APC_PMIE | PDMA_GO;
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
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ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
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ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
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cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
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ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
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(cfg | PLAYBACK_ENABLE));
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} else {
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#ifdef AUDIO_DEBUG
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snprintb(bits, sizeof(bits), APC_BITS, csr);
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#endif
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DPRINTF(("trigger_output: already: csr=%s\n", bits));
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}
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/* load next block if we can */
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csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
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if (csr & APC_PD) {
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cs4231_transfer_advance(t, &dmaaddr, &dmasize);
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNVA, dmaaddr);
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNC, dmasize);
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DPRINTF(("trigger_output: 2nd: %x %d, %x %d\n",
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PC),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_PNC)));
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}
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return 0;
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}
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static int
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cs4231_sbus_halt_output(void *addr)
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{
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struct cs4231_sbus_softc *sbsc;
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struct cs4231_softc *sc;
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uint32_t csr;
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int cfg;
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#ifdef AUDIO_DEBUG
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char bits[128];
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#endif
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sbsc = addr;
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sc = &sbsc->sc_cs4231;
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sc->sc_playback.t_active = 0;
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csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
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#ifdef AUDIO_DEBUG
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snprintb(bits, sizeof(bits), APC_BITS, csr);
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#endif
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DPRINTF(("halt_output: csr=%s\n", bits));
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csr &= ~APC_INTR_MASK; /* do not clear interrupts accidentally */
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csr |= APC_PPAUSE; /* pause playback (let current complete) */
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
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/* let the curernt transfer complete */
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if (csr & PDMA_GO)
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do {
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csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh,
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APC_DMA_CSR);
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#ifdef AUDIO_DEBUG
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snprintb(bits, sizeof(bits), APC_BITS, csr);
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#endif
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DPRINTF(("halt_output: csr=%s\n", bits));
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} while ((csr & APC_PM) == 0);
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cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
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ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,(cfg & ~PLAYBACK_ENABLE));
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return 0;
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}
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/* NB: we don't enable APC_CMIE and won't use APC_CM */
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static int
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cs4231_sbus_trigger_input(void *addr, void *start, void *end, int blksize,
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void (*intr)(void *), void *arg,
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const audio_params_t *param)
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{
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struct cs4231_sbus_softc *sbsc;
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struct cs4231_softc *sc;
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struct cs_transfer *t;
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uint32_t csr;
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bus_addr_t dmaaddr;
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bus_size_t dmasize;
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int ret;
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#ifdef AUDIO_DEBUG
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char bits[128];
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#endif
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sbsc = addr;
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sc = &sbsc->sc_cs4231;
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t = &sc->sc_capture;
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ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
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start, end, blksize, intr, arg);
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if (ret != 0)
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return ret;
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csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
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#ifdef AUDIO_DEBUG
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snprintb(bits, sizeof(bits), APC_BITS, csr);
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#endif
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DPRINTF(("trigger_input: csr=%s\n", bits));
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DPRINTF(("trigger_input: was: %x %d, %x %d\n",
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CC),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNC)));
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/* supply first block */
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNVA, dmaaddr);
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNC, dmasize);
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DPRINTF(("trigger_input: 1st: %x %d, %x %d\n",
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CC),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNVA),
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bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNC)));
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csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
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if ((csr & CDMA_GO) == 0 || (csr & APC_CPAUSE) != 0) {
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int cfg;
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csr &= ~(APC_CPAUSE | APC_CMIE | APC_INTR_MASK);
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
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csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
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csr &= ~APC_INTR_MASK;
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csr |= APC_ENABLE | APC_CIE | CDMA_GO;
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bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
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ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
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ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
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cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
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ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
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(cfg | CAPTURE_ENABLE));
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} else {
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#ifdef AUDIO_DEBUG
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snprintb(bits, sizeof(bits), APC_BITS, csr);
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#endif
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DPRINTF(("trigger_input: already: csr=%s\n", bits));
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|
}
|
|
|
|
/* supply next block if we can */
|
|
csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
|
|
if (csr & APC_CD) {
|
|
cs4231_transfer_advance(t, &dmaaddr, &dmasize);
|
|
bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNVA, dmaaddr);
|
|
bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNC, dmasize);
|
|
DPRINTF(("trigger_input: 2nd: %x %d, %x %d\n",
|
|
bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CVA),
|
|
bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CC),
|
|
bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNVA),
|
|
bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CNC)));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int
|
|
cs4231_sbus_halt_input(void *addr)
|
|
{
|
|
struct cs4231_sbus_softc *sbsc;
|
|
struct cs4231_softc *sc;
|
|
uint32_t csr;
|
|
int cfg;
|
|
#ifdef AUDIO_DEBUG
|
|
char bits[128];
|
|
#endif
|
|
|
|
sbsc = addr;
|
|
sc = &sbsc->sc_cs4231;
|
|
sc->sc_capture.t_active = 0;
|
|
|
|
csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
|
|
#ifdef AUDIO_DEBUG
|
|
snprintb(bits, sizeof(bits), APC_BITS, csr);
|
|
#endif
|
|
DPRINTF(("halt_input: csr=%s\n", bits));
|
|
|
|
|
|
csr &= ~APC_INTR_MASK; /* do not clear interrupts accidentally */
|
|
csr |= APC_CPAUSE;
|
|
bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
|
|
|
|
/* let the curernt transfer complete */
|
|
if (csr & CDMA_GO)
|
|
do {
|
|
csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh,
|
|
APC_DMA_CSR);
|
|
#ifdef AUDIO_DEBUG
|
|
snprintb(bits, sizeof(bits), APC_BITS, csr);
|
|
#endif
|
|
DPRINTF(("halt_input: csr=%s\n", bits));
|
|
|
|
|
|
} while ((csr & APC_CM) == 0);
|
|
|
|
cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
|
|
ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, (cfg & ~CAPTURE_ENABLE));
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int
|
|
cs4231_sbus_intr(void *arg)
|
|
{
|
|
struct cs4231_sbus_softc *sbsc;
|
|
struct cs4231_softc *sc;
|
|
uint32_t csr;
|
|
int status;
|
|
bus_addr_t dmaaddr;
|
|
bus_size_t dmasize;
|
|
int served;
|
|
#if defined(AUDIO_DEBUG) || defined(DIAGNOSTIC)
|
|
char bits[128];
|
|
#endif
|
|
|
|
sbsc = arg;
|
|
sc = &sbsc->sc_cs4231;
|
|
csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR);
|
|
if ((csr & APC_INTR_MASK) == 0) /* any interrupt pending? */
|
|
return 0;
|
|
|
|
mutex_spin_enter(&sc->sc_ad1848.sc_intr_lock);
|
|
|
|
/* write back DMA status to clear interrupt */
|
|
bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, APC_DMA_CSR, csr);
|
|
++sc->sc_intrcnt.ev_count;
|
|
served = 0;
|
|
|
|
#ifdef AUDIO_DEBUG
|
|
if (cs4231_sbus_debug > 1)
|
|
cs4231_sbus_regdump("audiointr", sbsc);
|
|
#endif
|
|
|
|
status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
|
|
#ifdef AUDIO_DEBUG
|
|
snprintb(bits, sizeof(bits), AD_R2_BITS, status);
|
|
#endif
|
|
DPRINTF(("%s: status: %s\n", device_xname(sc->sc_ad1848.sc_dev),
|
|
bits));
|
|
if (status & INTERRUPT_STATUS) {
|
|
#ifdef AUDIO_DEBUG
|
|
int reason;
|
|
|
|
reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
|
|
snprintb(bits, sizeof(bits), CS_I24_BITS, reason);
|
|
DPRINTF(("%s: i24: %s\n", device_xname(sc->sc_ad1848.sc_dev),
|
|
bits));
|
|
#endif
|
|
/* clear ad1848 interrupt */
|
|
ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
|
|
}
|
|
|
|
if (csr & APC_CI) {
|
|
if (csr & APC_CD) { /* can supply new block */
|
|
struct cs_transfer *t = &sc->sc_capture;
|
|
|
|
cs4231_transfer_advance(t, &dmaaddr, &dmasize);
|
|
bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh,
|
|
APC_DMA_CNVA, dmaaddr);
|
|
bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh,
|
|
APC_DMA_CNC, dmasize);
|
|
|
|
if (t->t_intr != NULL)
|
|
sparc_softintr_schedule(sbsc->sc_rint);
|
|
++t->t_intrcnt.ev_count;
|
|
served = 1;
|
|
}
|
|
}
|
|
|
|
if (csr & APC_PMI) {
|
|
if (!sc->sc_playback.t_active)
|
|
served = 1; /* draining in halt_output() */
|
|
}
|
|
|
|
if (csr & APC_PI) {
|
|
if (csr & APC_PD) { /* can load new block */
|
|
struct cs_transfer *t = &sc->sc_playback;
|
|
|
|
if (t->t_active) {
|
|
cs4231_transfer_advance(t, &dmaaddr, &dmasize);
|
|
bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh,
|
|
APC_DMA_PNVA, dmaaddr);
|
|
bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh,
|
|
APC_DMA_PNC, dmasize);
|
|
}
|
|
|
|
if (t->t_intr != NULL)
|
|
sparc_softintr_schedule(sbsc->sc_pint);
|
|
++t->t_intrcnt.ev_count;
|
|
served = 1;
|
|
}
|
|
}
|
|
|
|
/* got an interrupt we don't know how to handle */
|
|
if (!served) {
|
|
#ifdef DIAGNOSTIC
|
|
snprintb(bits, sizeof(bits), APC_BITS, csr);
|
|
printf("%s: unhandled csr=%s\n",
|
|
device_xname(sc->sc_ad1848.sc_dev), bits);
|
|
#endif
|
|
/* evcnt? */
|
|
}
|
|
|
|
mutex_spin_exit(&sc->sc_ad1848.sc_intr_lock);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
cs4231_sbus_pint(void *cookie)
|
|
{
|
|
struct cs4231_softc *sc = cookie;
|
|
struct cs_transfer *t;
|
|
|
|
mutex_spin_enter(&sc->sc_ad1848.sc_intr_lock);
|
|
t = &sc->sc_playback;
|
|
if (t->t_intr != NULL)
|
|
(*t->t_intr)(t->t_arg);
|
|
mutex_spin_exit(&sc->sc_ad1848.sc_intr_lock);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
cs4231_sbus_rint(void *cookie)
|
|
{
|
|
struct cs4231_softc *sc = cookie;
|
|
struct cs_transfer *t;
|
|
|
|
mutex_spin_enter(&sc->sc_ad1848.sc_intr_lock);
|
|
t = &sc->sc_capture;
|
|
if (t->t_intr != NULL)
|
|
(*t->t_intr)(t->t_arg);
|
|
mutex_spin_exit(&sc->sc_ad1848.sc_intr_lock);
|
|
return 0;
|
|
}
|
|
|
|
#endif /* NAUDIO > 0 */
|