90 lines
3.2 KiB
C
90 lines
3.2 KiB
C
/* $NetBSD: rs5c313reg.h,v 1.3 2010/04/06 15:29:19 nonaka Exp $ */
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/*-
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* Copyright (c) 2005 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_RS5C313REG_H_
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#define _DEV_IC_RS5C313REG_H_
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/*
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* RICOH RS5C3[12]x Real Time Clock
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*/
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/* 5c313/5c314 don't have bank1 */
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#define RS5C313_SEC1 0 /* bank0 */
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#define RS5C313_SEC10 1 /* bank0 */
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#define RS5C313_MIN1 2 /* bank0 */
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#define RS5C313_MIN10 3 /* bank0 */
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#define RS5C313_HOUR1 4 /* bank0 */
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#define RS5C313_HOUR10 5 /* bank0 */
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#define RS5C313_WDAY 6 /* bank0 */
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#define RS5C313_TINT 7 /* bank0/1 (5c313/5c314/5c316/5c317) */
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#define RS5C313_SCRATCH 7 /* bank0/1 (5c321) */
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#define RS5C313_DAY1 8 /* bank0 */
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#define RS5C313_DAY10 9 /* bank0 */
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#define RS5C313_MON1 10 /* bank0 */
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#define RS5C313_MON10 11 /* bank0 */
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#define RS5C313_YEAR1 12 /* bank0 */
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#define RS5C313_YEAR10 13 /* bank0 */
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#define RS5C313_CTRL 14 /* bank0/1 */
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#define RS5C313_CTRL2 15 /* bank0/1 */
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/* Alarm register (5c316/5c317) */
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#define RS5C313_AWOD1 0 /* bank1 */
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#define RS5C313_AWOD2 1 /* bank1 */
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#define RS5C313_AMIN1 2 /* bank1 */
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#define RS5C313_AMIN10 3 /* bank1 */
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#define RS5C313_AHOUR1 4 /* bank1 */
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#define RS5C313_AHOUR10 5 /* bank1 */
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/* Timer register (5c317) */
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#define RS5C313_TMR 9 /* bank1 */
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/* 32kHz control register (5c317/5c321) */
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#define RS5C313_32KHZ 10 /* bank1 */
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/* TINT register */
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#define TINT_CT0 0x01
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#define TINT_CT1 0x02
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#define TINT_CT2 0x04
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#define TINT_CT3 0x08
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/* CTRL register */
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#define CTRL_BSY 0x01 /* read */
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#define CTRL_ADJ 0x01 /* write */
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#define CTRL_XSTP 0x02 /* read */
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#define CTRL_WTEN 0x02 /* write */
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#define CTRL_24H 0x04 /* read/write (5c313/5c314) */
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#define CTRL_ALFG 0x04 /* read/write (5c316/5c317) */
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#define CTRL_CTFG 0x08 /* read/write */
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/* CTRL2 register */
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#define CTRL2_NTEST 0x01
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#define CTRL2_BANK 0x02 /* (5c316/5c317/5c321) */
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#define CTRL2_TMR 0x04 /* (5c317) */
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#define CTRL2_24H 0x08 /* (5c316/5c317/5c321) */
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#endif /* _DEV_IC_RS5C313REG_H_ */
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