521 lines
15 KiB
C
521 lines
15 KiB
C
/* $NetBSD: mlxreg.h,v 1.8 2008/09/08 23:36:54 gmcgarry Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Andrew Doran.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1999 Michael Smith
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from FreeBSD: mlxreg.h,v 1.5.2.2 2000/04/24 19:40:50 msmith Exp
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*/
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#ifndef _IC_MLXREG_H_
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#define _IC_MLXREG_H_
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#define MLX_SECTOR_SIZE 512
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/*
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* Selected command codes.
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*/
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#define MLX_CMD_ENQUIRY_OLD 0x05
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#define MLX_CMD_ENQUIRY 0x53
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#define MLX_CMD_ENQUIRY2 0x1c
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#define MLX_CMD_ENQSYSDRIVE 0x19
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#define MLX_CMD_READSG 0xb6
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#define MLX_CMD_WRITESG 0xb7
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#define MLX_CMD_READSG_OLD 0x82
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#define MLX_CMD_WRITESG_OLD 0x83
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#define MLX_CMD_FLUSH 0x0a
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#define MLX_CMD_LOGOP 0x72
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#define MLX_CMD_REBUILDASYNC 0x16
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#define MLX_CMD_CHECKASYNC 0x1e
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#define MLX_CMD_REBUILDSTAT 0x0c
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#define MLX_CMD_STOPCHANNEL 0x13
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#define MLX_CMD_STARTCHANNEL 0x12
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#define MLX_CMD_READ_CONFIG 0x4e
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#define MLX_CMD_WRITE_CONFIG 0x4f
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#define MLX_CMD_READ_DK_CONFIG 0x4a
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#define MLX_CMD_WRITE_DK_CONFIG 0x4b
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#define MLX_CMD_DIRECT_CDB 0x04
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#define MLX_CMD_DEVICE_STATE 0x50
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#define MLX_CMD_READ_CONFIG2 0x3d
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#define MLX_CMD_WRITE_CONFIG2 0x3c
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#ifdef _KERNEL
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/*
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* Status values.
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*/
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#define MLX_STATUS_OK 0x0000
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#define MLX_STATUS_RDWROFFLINE 0x0002 /* read/write claims drive is offline */
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#define MLX_STATUS_WEDGED 0xdeaf /* controller not listening */
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#define MLX_STATUS_LOST 0xdead /* never came back */
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#define MLX_STATUS_BUSY 0xbabe /* command is in controller */
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/*
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* V1 (EISA) interface.
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*/
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#define MLX_V1REG_IE 0x09
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#define MLX_V1REG_IDB 0x0d
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#define MLX_V1REG_ODB_EN 0x0e
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#define MLX_V1REG_ODB 0x0f
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#define MLX_V1REG_MAILBOX 0x10
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#define MLX_V1_IDB_FULL 0x01 /* mailbox is full */
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#define MLX_V1_IDB_INIT_BUSY 0x02 /* init in progress */
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#define MLX_V1_IDB_SACK 0x02 /* acknowledge status read */
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#define MLX_V1_IDB_RESET 0x10 /* reset controller */
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#define MLX_V1_ODB_SAVAIL 0x01 /* status is available */
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#define MLX_V1_ODB_RESET 0x02 /* reset controller */
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#define MLX_V1_FWERROR_PEND 0x04 /* firmware error pending */
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/*
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* V2/V3 interface.
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*/
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#define MLX_V3REG_MAILBOX 0x00
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#define MLX_V3REG_STATUS_IDENT 0x0d
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#define MLX_V3REG_STATUS 0x0e
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#define MLX_V3REG_IDB 0x40
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#define MLX_V3REG_ODB 0x41
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#define MLX_V3REG_IE 0x43
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#define MLX_V3REG_FWERROR 0x3f
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#define MLX_V3REG_FWERROR_PARAM1 0x00
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#define MLX_V3REG_FWERROR_PARAM2 0x01
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#define MLX_V3_IDB_FULL 0x01 /* mailbox is full */
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#define MLX_V3_IDB_INIT_BUSY 0x02 /* init in progress */
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#define MLX_V3_IDB_SACK 0x02 /* acknowledge status read */
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#define MLX_V3_IDB_RESET 0x08 /* reset controller */
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#define MLX_V3_ODB_SAVAIL 0x01 /* status is available */
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#define MLX_V3_FWERROR_PEND 0x04 /* firmware error pending */
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/*
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* V4 interface.
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*/
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#define MLX_V4REG_MAILBOX 0x1000
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#define MLX_V4REG_STATUS_IDENT 0x1018
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#define MLX_V4REG_STATUS 0x101a
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#define MLX_V4REG_IDB 0x0020
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#define MLX_V4REG_ODB 0x002c
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#define MLX_V4REG_IE 0x0034
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#define MLX_V4REG_FWERROR 0x103f
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#define MLX_V4REG_FWERROR_PARAM1 0x1000
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#define MLX_V4REG_FWERROR_PARAM2 0x1001
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#define MLX_V4_IDB_FULL 0x01 /* mailbox is full */
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#define MLX_V4_IDB_INIT_BUSY 0x02 /* initialisation in progress */
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#define MLX_V4_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */
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#define MLX_V4_IDB_SACK 0x02 /* acknowledge status read */
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#define MLX_V4_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */
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#define MLX_V4_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */
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#define MLX_V4_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */
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#define MLX_V4_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */
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#define MLX_V4_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */
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#define MLX_V4_IE_MASK 0xfb /* message unit interrupt mask */
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#define MLX_V4_IE_DISINT 0x04 /* interrupt disable bit */
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#define MLX_V4_FWERROR_PEND 0x04 /* firmware error pending */
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/*
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* V5 interface.
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*/
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#define MLX_V5REG_MAILBOX 0x50
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#define MLX_V5REG_STATUS_IDENT 0x5d
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#define MLX_V5REG_STATUS 0x5e
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#define MLX_V5REG_IDB 0x60
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#define MLX_V5REG_ODB 0x61
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#define MLX_V5REG_IE 0x34
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#define MLX_V5REG_FWERROR 0x63
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#define MLX_V5REG_FWERROR_PARAM1 0x50
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#define MLX_V5REG_FWERROR_PARAM2 0x51
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#define MLX_V5_IDB_EMPTY 0x01 /* mailbox is empty */
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#define MLX_V5_IDB_INIT_DONE 0x02 /* initialisation has completed */
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#define MLX_V5_IDB_HWMBOX_CMD 0x01 /* posted hardware mailbox command */
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#define MLX_V5_IDB_SACK 0x02 /* acknowledge status read */
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#define MLX_V5_IDB_RESET 0x08 /* reset request */
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#define MLX_V5_IDB_MEMMBOX_CMD 0x10 /* posted memory mailbox command */
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#define MLX_V5_ODB_HWSAVAIL 0x01 /* status available for hardware m/b */
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#define MLX_V5_ODB_MEMSAVAIL 0x02 /* status available for memory m/b */
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#define MLX_V5_ODB_HWMBOX_ACK 0x01 /* ack status read from hardware m/b */
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#define MLX_V5_ODB_MEMMBOX_ACK 0x02 /* ack status read from memory m/b */
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#define MLX_V5_IE_DISINT 0x04 /* interrupt disable bit */
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#define MLX_V5_FWERROR_PEND 0x04 /* firmware error pending */
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#endif /* _KERNEL */
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/*
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* Scatter-gather list format, type 1, kind 00.
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*/
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struct mlx_sgentry {
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u_int32_t sge_addr;
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u_int32_t sge_count;
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} __packed;
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/*
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* Command result buffers, as placed in system memory by the controller.
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*/
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struct mlx_enquiry_old {
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u_int8_t me_num_sys_drvs;
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u_int8_t me_res1[3];
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u_int32_t me_drvsize[8];
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u_int16_t me_flash_age;
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u_int8_t me_status_flags;
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u_int8_t me_free_state_change_count;
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u_int8_t me_fwminor;
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u_int8_t me_fwmajor;
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u_int8_t me_rebuild_flag;
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u_int8_t me_max_commands;
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u_int8_t me_offline_sd_count;
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u_int8_t me_res3;
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u_int8_t me_critical_sd_count;
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u_int8_t me_res4[3];
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u_int8_t me_dead_count;
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u_int8_t me_res5;
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u_int8_t me_rebuild_count;
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u_int8_t me_misc_flags;
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struct {
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u_int8_t dd_targ;
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u_int8_t dd_chan;
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} __packed me_dead[20];
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} __packed;
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struct mlx_enquiry {
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u_int8_t me_num_sys_drvs;
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u_int8_t me_res1[3];
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u_int32_t me_drvsize[32];
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u_int16_t me_flash_age;
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u_int8_t me_status_flags;
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#define MLX_ENQ_SFLAG_DEFWRERR 0x01 /* deferred write error indicator */
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#define MLX_ENQ_SFLAG_BATTLOW 0x02 /* battery low */
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u_int8_t me_res2;
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u_int8_t me_fwminor;
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u_int8_t me_fwmajor;
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u_int8_t me_rebuild_flag;
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u_int8_t me_max_commands;
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u_int8_t me_offline_sd_count;
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u_int8_t me_res3;
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u_int16_t me_event_log_seq_num;
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u_int8_t me_critical_sd_count;
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u_int8_t me_res4[3];
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u_int8_t me_dead_count;
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u_int8_t me_res5;
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u_int8_t me_rebuild_count;
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u_int8_t me_misc_flags;
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#define MLX_ENQ_MISC_BBU 0x08 /* battery backup present */
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struct {
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u_int8_t dd_targ;
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u_int8_t dd_chan;
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} __packed me_dead[20];
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} __packed;
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struct mlx_enquiry2 {
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u_int8_t me_hardware_id[4];
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u_int8_t me_firmware_id[4];
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u_int32_t me_res1;
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u_int8_t me_configured_channels;
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u_int8_t me_actual_channels;
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u_int8_t me_max_targets;
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u_int8_t me_max_tags;
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u_int8_t me_max_sys_drives;
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u_int8_t me_max_arms;
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u_int8_t me_max_spans;
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u_int8_t me_res2;
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u_int32_t me_res3;
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u_int32_t me_mem_size;
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u_int32_t me_cache_size;
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u_int32_t me_flash_size;
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u_int32_t me_nvram_size;
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u_int16_t me_mem_type;
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u_int16_t me_clock_speed;
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u_int16_t me_mem_speed;
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u_int16_t me_hardware_speed;
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u_int8_t me_res4[12];
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u_int16_t me_max_commands;
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u_int16_t me_max_sg;
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u_int16_t me_max_dp;
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u_int16_t me_max_iod;
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u_int16_t me_max_comb;
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u_int8_t me_latency;
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u_int8_t me_res5;
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u_int8_t me_scsi_timeout;
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u_int8_t me_res6;
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u_int16_t me_min_freelines;
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u_int8_t me_res7[8];
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u_int8_t me_rate_const;
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u_int8_t me_res8[11];
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u_int16_t me_physblk;
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u_int16_t me_logblk;
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u_int16_t me_maxblk;
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u_int16_t me_blocking_factor;
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u_int16_t me_cacheline;
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u_int8_t me_scsi_cap;
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u_int8_t me_res9[5];
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u_int16_t me_firmware_build;
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u_int8_t me_fault_mgmt_type;
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u_int8_t me_res10;
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u_int32_t me_firmware_features;
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u_int8_t me_res11[8];
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} __packed;
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/* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these. */
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struct mlx_enq_sys_drive {
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u_int32_t sd_size;
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u_int8_t sd_state;
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u_int8_t sd_raidlevel;
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u_int16_t sd_res1;
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} __packed;
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/*
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* MLX_CMD_LOGOP/MLX_LOGOP_GET
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*
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* Bitfields:
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*
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* 0-4 el_target SCSI target
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* 5-7 el_target SCSI channel
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* 0-6 el_errorcode error code
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* 7-7 el_errorcode validity (?)
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* 0-3 el_sense sense key
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* 4-4 el_sense reserved
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* 5-5 el_sense ILI
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* 6-6 el_sense EOM
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* 7-7 el_sense filemark
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*/
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struct mlx_eventlog_entry {
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u_int8_t el_type;
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u_int8_t el_length;
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u_int8_t el_target;
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u_int8_t el_lun;
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u_int16_t el_seqno;
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u_int8_t el_errorcode;
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u_int8_t el_segment;
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u_int8_t el_sense;
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u_int8_t el_information[4];
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u_int8_t el_addsense;
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u_int8_t el_csi[4];
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u_int8_t el_asc;
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u_int8_t el_asq;
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u_int8_t el_res3[12];
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} __packed;
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#define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */
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#define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */
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struct mlx_rebuild_stat {
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u_int32_t rb_drive;
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u_int32_t rb_size;
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u_int32_t rb_remaining;
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} __packed;
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struct mlx_config {
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u_int16_t cf_flags1;
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#define MLX_CF2_ACTV_NEG 0x0002
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#define MLX_CF2_NORSTRTRY 0x0080
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#define MLX_CF2_STRGWRK 0x0100
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#define MLX_CF2_HPSUPP 0x0200
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#define MLX_CF2_NODISCN 0x0400
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#define MLX_CF2_ARM 0x2000
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#define MLX_CF2_OFM 0x8000
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#define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM)
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u_int8_t cf_oemid;
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u_int8_t cf_oem_model;
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u_int8_t cf_physical_sector;
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u_int8_t cf_logical_sector;
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u_int8_t cf_blockfactor;
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u_int8_t cf_flags2;
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#define MLX_CF2_READAH 0x01
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#define MLX_CF2_BIOSDLY 0x02
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#define MLX_CF2_REASS1S 0x10
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#define MLX_CF2_FUAENABL 0x40
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#define MLX_CF2_R5ALLS 0x80
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u_int8_t cf_rcrate;
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u_int8_t cf_res1;
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u_int8_t cf_blocks_per_cache_line;
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u_int8_t cf_blocks_per_stripe;
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u_int8_t cf_scsi_param_0;
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u_int8_t cf_scsi_param_1;
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u_int8_t cf_scsi_param_2;
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u_int8_t cf_scsi_param_3;
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u_int8_t cf_scsi_param_4;
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u_int8_t cf_scsi_param_5;
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u_int8_t cf_scsi_initiator_id;
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u_int8_t cf_res2;
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u_int8_t cf_startup_mode;
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u_int8_t cf_simultaneous_spinup_devices;
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u_int8_t cf_delay_between_spinups;
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u_int8_t cf_res3;
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u_int16_t cf_checksum;
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} __packed;
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struct mlx_config2 {
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struct mlx_config cf2_cf;
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u_int8_t cf2_reserved0[26];
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u_int8_t cf2_flags;
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#define MLX_CF2_BIOS_DIS 0x01
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#define MLX_CF2_CDROM_DIS 0x02
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#define MLX_CF2_GEOM_255 0x20
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u_int8_t cf2_reserved1[9];
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u_int16_t cf2_checksum;
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} __packed;
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struct mlx_sys_drv_span {
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u_int32_t sp_start_lba;
|
|
u_int32_t sp_nblks;
|
|
u_int8_t sp_arm[8];
|
|
} __packed;
|
|
|
|
struct mlx_sys_drv {
|
|
u_int8_t sd_status;
|
|
u_int8_t sd_ext_status;
|
|
u_int8_t sd_mod1;
|
|
u_int8_t sd_mod2;
|
|
u_int8_t sd_raidlevel;
|
|
#define MLX_SYS_DRV_WRITEBACK (1<<7)
|
|
#define MLX_SYS_DRV_RAID0 0
|
|
#define MLX_SYS_DRV_RAID1 1
|
|
#define MLX_SYS_DRV_RAID3 3
|
|
#define MLX_SYS_DRV_RAID5 5
|
|
#define MLX_SYS_DRV_RAID6 6
|
|
#define MLX_SYS_DRV_JBOD 7
|
|
u_int8_t sd_valid_arms;
|
|
u_int8_t sd_valid_spans;
|
|
u_int8_t sd_init_state;
|
|
#define MLX_SYS_DRV_INITTED 0x81;
|
|
struct mlx_sys_drv_span sd_span[4];
|
|
} __packed;
|
|
|
|
struct mlx_phys_drv {
|
|
u_int8_t pd_flags1;
|
|
#define MLX_PHYS_DRV_PRESENT 0x01
|
|
u_int8_t pd_flags2;
|
|
#define MLX_PHYS_DRV_OTHER 0x00
|
|
#define MLX_PHYS_DRV_DISK 0x01
|
|
#define MLX_PHYS_DRV_SEQUENTIAL 0x02
|
|
#define MLX_PHYS_DRV_CDROM 0x03
|
|
#define MLX_PHYS_DRV_FAST20 0x08
|
|
#define MLX_PHYS_DRV_SYNC 0x10
|
|
#define MLX_PHYS_DRV_FAST 0x20
|
|
#define MLX_PHYS_DRV_WIDE 0x40
|
|
#define MLX_PHYS_DRV_TAG 0x80
|
|
u_int8_t pd_status;
|
|
#define MLX_PHYS_DRV_DEAD 0x00
|
|
#define MLX_PHYS_DRV_WRONLY 0x02
|
|
#define MLX_PHYS_DRV_ONLINE 0x03
|
|
#define MLX_PHYS_DRV_STANDBY 0x10
|
|
u_int8_t pd_res1;
|
|
u_int8_t pd_period;
|
|
u_int8_t pd_offset;
|
|
u_int32_t pd_config_size;
|
|
} __packed;
|
|
|
|
struct mlx_core_cfg {
|
|
u_int8_t cc_num_sys_drives;
|
|
u_int8_t cc_res1[3];
|
|
struct mlx_sys_drv cc_sys_drives[32];
|
|
struct mlx_phys_drv cc_phys_drives[5 * 16];
|
|
} __packed;
|
|
|
|
/*
|
|
* Bitfields:
|
|
*
|
|
* 0-3 dcdb_target SCSI target
|
|
* 4-7 dcdb_target SCSI channel
|
|
* 0-3 dcdb_length CDB length
|
|
* 4-7 dcdb_length high 4 bits of `datasize'
|
|
*/
|
|
struct mlx_dcdb {
|
|
u_int8_t dcdb_target;
|
|
u_int8_t dcdb_flags;
|
|
#define MLX_DCDB_NO_DATA 0x00
|
|
#define MLX_DCDB_DATA_IN 0x01
|
|
#define MLX_DCDB_DATA_OUT 0x02
|
|
#define MLX_DCDB_EARLY_STATUS 0x04
|
|
#define MLX_DCDB_TIMEOUT_10S 0x10 /* This lot is wrong? [ad] */
|
|
#define MLX_DCDB_TIMEOUT_60S 0x20
|
|
#define MLX_DCDB_TIMEOUT_20M 0x30
|
|
#define MLX_DCDB_TIMEOUT_24H 0x40
|
|
#define MLX_DCDB_NO_AUTO_SENSE 0x40 /* XXX ?? */
|
|
#define MLX_DCDB_DISCONNECT 0x80
|
|
u_int16_t dcdb_datasize;
|
|
u_int32_t dcdb_physaddr;
|
|
u_int8_t dcdb_length;
|
|
u_int8_t dcdb_sense_length;
|
|
u_int8_t dcdb_cdb[12];
|
|
u_int8_t dcdb_sense[64];
|
|
u_int8_t dcdb_status;
|
|
u_int8_t res1;
|
|
} __packed;
|
|
|
|
struct mlx_bbtable_entry {
|
|
u_int32_t bbt_block_number;
|
|
u_int8_t bbt_extent;
|
|
u_int8_t bbt_res1;
|
|
u_int8_t bbt_entry_type;
|
|
u_int8_t bbt_system_drive; /* high 3 bits reserved */
|
|
} __packed;
|
|
|
|
#endif /* !_IC_MLXREG_H_ */
|