168 lines
6.8 KiB
C
168 lines
6.8 KiB
C
/* $NetBSD: mc68450reg.h,v 1.5 2008/04/28 20:23:50 martin Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Minoura Makoto.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Motorola MC68450 DMAC register definition.
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*/
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#define DMAC_NCHAN 4 /* Number of channels */
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#define DMAC_CHAN_SIZE 0x40 /* I/O area size per channes */
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/* register location per channel */
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#define DMAC_REG_CSR 0x00 /* Channel Status Register */
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#define DMAC_REG_CER 0x01 /* Channel Error Register */
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#define DMAC_REG_DCR 0x04 /* Device Control Register */
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#define DMAC_REG_OCR 0x05 /* Operation Control Register */
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#define DMAC_REG_SCR 0x06 /* Sequence Control Register */
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#define DMAC_REG_CCR 0x07 /* Channel Control Register */
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#define DMAC_REG_MTCR 0x0a /* Memory Transfer Count Register */
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#define DMAC_REG_MAR 0x0c /* Memory Address Register */
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#define DMAC_REG_DAR 0x14 /* Device Address Register */
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#define DMAC_REG_BTCR 0x1a /* Base Transfer Count Register */
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#define DMAC_REG_BAR 0x1c /* Base Address Register */
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#define DMAC_REG_NIVR 0x25 /* Normal Interrupt Vector Register */
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#define DMAC_REG_EIVR 0x27 /* Error Interrupt Vector Register */
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#define DMAC_REG_MFCR 0x29 /* Memory Function Code Register */
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#define DMAC_REG_CPR 0x2d /* Channel Priority Register */
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#define DMAC_REG_DFCR 0x31 /* Device Function Code Register */
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#define DMAC_REG_BFCR 0x39 /* Base Function Code Register */
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#define DMAC_REG_GCR 0x3f /* General Control Register */
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/* CSR bits */
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#define DMAC_CSR_COC 0x80 /* Channel Operation Complete */
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#define DMAC_CSR_BTC 0x40 /* Block Transfer Complete */
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#define DMAC_CSR_NDT 0x20 /* Normal Device Termination */
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#define DMAC_CSR_ERR 0x10 /* Error */
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#define DMAC_CSR_ACT 0x08 /* Channel Active */
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#define DMAC_CSR_PCT 0x02 /* PCL Transition */
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#define DMAC_CSR_PCS 0x01 /* PCL Level */
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/* CER meanings */
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/*
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* 0x00: No error
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* 0x01: Configuration error
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* 0x02: Operation timing error
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* 0x05: Address error in memory transfer
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* 0x06: Address error in device transfer
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* 0x07: Address error in base address reading
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* 0x09: Bus error in memory transfer
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* 0x0a: Bus error in device transfer
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* 0x0b: Bus error in base address reading
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* 0x0d: Count error in memory transfer count
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* 0x0e: Count error in device transfer count
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* 0x0f: Count error in base address
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* 0x10: External abort
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* 0x11: Software abort
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*/
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/* DCR bits */
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#define DMAC_DCR_XRM_MASK 0xc0
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#define DMAC_DCR_XRM_BURST 0x00 /* Burst mode */
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#define DMAC_DCR_XRM_CSWOH 0x80 /* Cycle steal w/o hold */
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#define DMAC_DCR_XRM_CSWH 0xc0 /* Cycle steal w/ hold */
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#define DMAC_DCR_OTYP_MASK 0x30
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#define DMAC_DCR_OTYP_EASYNC 0x00 /* Explicit M68000 */
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#define DMAC_DCR_OTYP_ESYNC 0x10 /* Explicit M6800 */
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#define DMAC_DCR_OTYP_IA 0x20 /* Implicit with ack */
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#define DMAC_DCR_OTYP_IAR 0x30 /* Implicit with ack and rdy */
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#define DMAC_DCR_OPS_MASK 0x08
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#define DMAC_DCR_OPS_8BIT 0x00 /* 8bit */
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#define DMAC_DCR_OPS_16BIT 0x08 /* 16bit */
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#define DMAC_DCR_PCL_MASK 0x03
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#define DMAC_DCR_PCL_STATUS 0x00
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#define DMAC_DCR_PCL_INTERRUPT 0x01
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#define DMAC_DCR_PCL_STARTPLS 0x02
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#define DMAC_DCR_PCL_ABORT 0x03
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/* OCR bits */
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#define DMAC_OCR_DIR_MASK 0x80
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#define DMAC_OCR_DIR_MTD 0x00 /* Direction: memory to device */
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#define DMAC_OCR_DIR_DTM 0x80 /* Direction: device to memory */
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#define DMAC_OCR_SIZE_MASK 0x30
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#define DMAC_OCR_SIZE_BYTE 0x00 /* Size: byte */
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#define DMAC_OCR_SIZE_WORD 0x10 /* Size: word */
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#define DMAC_OCR_SIZE_LONGWORD 0x20 /* Size: longword */
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#define DMAC_OCR_SIZE_BYTE_NOPACK 0x30 /* Size: byte, no packing */
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#define DMAC_OCR_CHAIN_MASK 0x0c
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#define DMAC_OCR_CHAIN_DISABLED 0x00 /* Chain mode disabled */
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#define DMAC_OCR_CHAIN_ARRAY 0x08 /* Array chain mode */
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#define DMAC_OCR_CHAIN_LINKARRAY 0x0c /* Linked array chain mode */
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#define DMAC_OCR_REQG_MASK 0x03
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#define DMAC_OCR_REQG_LIMITED_RATE 0x00 /* Internal limited rate */
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#define DMAC_OCR_REQG_MAXIMUM_RATE 0x01 /* Internal maximum rate */
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#define DMAC_OCR_REQG_EXTERNAL 0x02 /* External */
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#define DMAC_OCR_REQG_AUTO_START 0x03 /* Auto start, external */
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/* SCR bits */
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#define DMAC_SCR_MAC_MASK 0x0c
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#define DMAC_SCR_MAC_NO_COUNT 0x00 /* Fixed memory address */
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#define DMAC_SCR_MAC_COUNT_UP 0x04 /* Memory address count up */
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#define DMAC_SCR_MAC_COUNT_DOWN 0x08 /* Memory address count down */
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#define DMAC_SCR_DAC_MASK 0x03
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#define DMAC_SCR_DAC_NO_COUNT 0x00 /* Fixed device address */
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#define DMAC_SCR_DAC_COUNT_UP 0x01 /* Device address count up */
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#define DMAC_SCR_DAC_COUNT_DOWN 0x02 /* Device address count down */
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/* CCR bits */
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#define DMAC_CCR_STR 0x80 /* Start channel */
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#define DMAC_CCR_CNT 0x40 /* Continue operation */
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#define DMAC_CCR_HLT 0x20 /* Software halt */
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#define DMAC_CCR_SAB 0x10 /* Software abort */
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#define DMAC_CCR_INT 0x08 /* Interrupt enable */
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/* GCR bits */
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#define DMAC_GCR_BT_MASK 0x0c
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#define DMAC_GCR_BT_16 0x00 /* 16clocks */
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#define DMAC_GCR_BT_32 0x04 /* 32clocks */
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#define DMAC_GCR_BT_64 0x08 /* 64clocks */
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#define DMAC_GCR_BT_128 0x0c /* 128clocks */
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#define DMAC_GCR_BR_MASK 0x03
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#define DMAC_GCR_BR_50 0x00 /* 50% bandwidth */
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#define DMAC_GCR_BR_25 0x01 /* 25% bandwidth */
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#define DMAC_GCR_BR_12 0x02 /* 12.5% bandwidth */
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#define DMAC_GCR_BR_6 0x03 /* 6.25% bandwidth */
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/* MFC/DFC function codes */
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#define DMAC_FC_USER_DATA 0x01
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#define DMAC_FC_USER_PROGRAM 0x02
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#define DMAC_FC_KERNEL_DATA 0x05
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#define DMAC_FC_KERNEL_PROGRAM 0x06
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#define DMAC_FC_CPU 0x07
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/*
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* An element of the array used in DMAC scatter-gather transfer
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* (array chaining mode)
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*/
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struct dmac_sg_array {
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u_int32_t da_addr;
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u_int16_t da_count;
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};
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