412 lines
13 KiB
C
412 lines
13 KiB
C
#ifndef INTERWAVEREG_H
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#define INTERWAVEREG_H
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/* $NetBSD: interwavereg.h,v 1.9 2008/04/28 20:23:50 martin Exp $ */
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/*
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* Author: Kari Mettinen
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define IW_LINELEVEL_MAX ((1L << 10) - 1)
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#define IW_LINELEVEL_CODEC_MAX ((1L << 10) - 1)
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#define IW_OUTPUT_CLASS 10
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#define IW_INPUT_CLASS 11
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#define IW_RECORD_CLASS 12
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#define IW_MIC_IN 11
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#define IW_MIC_IN_LVL 0
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/* these 2 are hw dependent values */
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#define IW_RIGHT_MIC_IN_PORT 0x16
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#define IW_LEFT_MIC_IN_PORT 0x17
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#define IW_AUX1 12
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#define IW_AUX1_LVL 1
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#define IW_RIGHT_AUX1_PORT 0x02
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#define IW_LEFT_AUX1_PORT 0x03
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#define IW_AUX2 13
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#define IW_AUX2_LVL 2
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#define IW_RIGHT_AUX2_PORT 0x04
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#define IW_LEFT_AUX2_PORT 0x05
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#define IW_LINE_IN 14
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#define IW_LINE_IN_LVL 3
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#define IW_RIGHT_LINE_IN_PORT 0x12
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#define IW_LEFT_LINE_IN_PORT 0x13
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#define IW_LINE_OUT 15
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#define IW_LINE_OUT_LVL 4
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#define IW_RIGHT_LINE_OUT_PORT 0x19
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#define IW_LEFT_LINE_OUT_PORT 0x1b
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#define IW_RECORD_SOURCE 5
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#define IW_REC 16
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#define IW_REC_LVL 6
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#define IW_REC_LEFT_PORT 0x00
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#define IW_REC_RIGHT_PORT 0x01
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#define IW_DAC 18
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#define IW_DAC_LVL 7
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#define IW_LEFT_DAC_PORT 0x06
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#define IW_RIGHT_DAC_PORT 0x07
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#define IW_LOOPBACK 19
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#define IW_LOOPBACK_LVL 8
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#define IW_LOOPBACK_PORT 0x0d
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#define IW_MONO_IN 20
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#define IW_MONO_IN_LVL 9
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#define IW_MONO_IN_PORT 0x1a
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#define IW_LINE_IN_SRC 0
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#define IW_AUX1_SRC 1
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#define IW_MIC_IN_SRC 2
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#define IW_MIX_OUT_SRC 3
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/* DMA flags */
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#define IW_PLAYBACK 1L
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#define IW_RECORD 2L
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#define ADDR_HIGH(a) (u_short)((a) >> 7)
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#define ADDR_LOW(a) (u_short)((a) << 9)
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#define MIDI_TX_IRQ 0x01
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#define MIDI_RX_IRQ 0x02
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#define ALIB_TIMER1_IRQ 0x04
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#define ALIB_TIMER2_IRQ 0x08
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#define UASBCI 0x45 /* UASBCI index */
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#define SAMPLE_CONTROL 0x49 /* Not used by IW */
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#define SET_VOICES 0x0E
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#define SAVI_WR 0x0E
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#define WAVETABLE_IRQ 0x20
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#define ENVELOPE_IRQ 0x40
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#define DMA_TC_IRQ 0x80
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#define GEN_INDEX 0x03 /* IGIDX offset into p3xr */
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#define VOICE_SELECT 0x02 /* SVSR offset into p3xr */
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#define VOICE_IRQS 0x8F /* SVII index (read) */
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#define URSTI 0x4C /* URSTI index */
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#define GF1_SET 0x01 /* URSTI[0] */
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#define GF1_OUT_ENABLE 0x02 /* URSTI[1] */
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#define GF1_IRQ_ENABLE 0x04 /* URSTI[2] */
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#define GF1_RESET 0xFE /* URSTI[0]=0 */
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#define VOICE_VOLUME_IRQ 0x04 /* SVII[2] */
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#define VOICE_WAVE_IRQ 0x08 /* SVII[3] */
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#define VC_IRQ_ENABLE 0x20 /* SACI[5] or SVCI[5]*/
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#define VOICE_NUMBER 0x1F /* Mask for SVII[4:0] */
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#define VC_IRQ_PENDING 0x80 /* SACI[7] or SVCI[7] */
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#define VC_DIRECT 0x40 /* SACI[6] or SVCI[6]*/
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#define VC_DATA_WIDTH 0x04 /* SACI[2] */
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#define VOICE_STOP 0x02 /* SACI[1] */
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#define VOICE_STOPPED 0x01 /* SACI[0] */
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#define VOLUME_STOP 0x02 /* SVCI[1] */
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#define VOLUME_STOPPED 0x01 /* SVCI[0] */
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#define VC_ROLLOVER 0x04 /* SVCI[2] */
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#define VC_LOOP_ENABLE 0x08 /* SVCI[3] or SACI[3]*/
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#define VC_BI_LOOP 0x10 /* SVCI[4] or SACI[4]*/
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#define VOICE_OFFSET 0x20 /* SMSI[5] */
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#define VOLUME_RATE0 0x00 /* SVRI[7:6]=(0,0) */
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#define VOLUME_RATE1 0x40 /* SVRI[7:6]=(0,1) */
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#define VOLUME_RATE2 0x80 /* SVRI[7:6]=(1,0) */
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#define VOLUME_RATE3 0xC0 /* SVRI[7:6]=(1,1) */
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#define CSR1R 0x02
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#define CPDR 0x03
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#define CRDR 0x03
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#define SHUT_DOWN 0x7E /* shuts InterWave down */
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#define POWER_UP 0xFE /* enables all modules */
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#define CODEC_PWR_UP 0x81 /* enables Codec Analog Ckts */
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#define CODEC_PWR_DOWN 0x01 /* disables Codec Analog Ckts */
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#define CODEC_REC_UP 0x82 /* Enables Record Path */
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#define CODEC_REC_DOWN 0x02 /* Disables Record Path */
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#define CODEC_PLAY_UP 0x84 /* Enables Playback Path */
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#define CODEC_PLAY_DOWN 0x04 /* Disables Playback Path */
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#define CODEC_IRQ_ENABLE 0x02 /* CEXTI[2] */
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#define CODEC_TIMER_IRQ 0x40 /* CSR3I[6] */
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#define CODEC_REC_IRQ 0x20 /* CSR3I[5] */
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#define CODEC_PLAY_IRQ 0x10 /* CSR3I[4] */
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#define CODEC_INT 0x01 /* CSR1R[0] */
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#define MONO_INPUT 0x80 /* CMONOI[7] */
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#define MONO_OUTPUT 0x40 /* CMONOI[6] */
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#define MIDI_UP 0x88 /* Enables MIDI ports */
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#define MIDI_DOWN 0x08 /* Disables MIDI ports */
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#define SYNTH_UP 0x90 /* Enables Synthesizer */
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#define SYNTH_DOWN 0x10 /* Disables Synthesizer */
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#define LMC_UP 0xA0 /* Enables LM Module */
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#define LMC_DOWN 0x20 /* Disbales LM Module */
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#define XTAL24_UP 0xC0 /* Enables 24MHz Osc */
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#define XTAL24_DOWN 0x40 /* Disables 24MHz Osc */
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#define PPWRI 0xF2 /* PPWRI index */
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#define PLAY 0x0F
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#define REC 0x1F
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#define LEFT_AUX1_INPUT 0x02
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#define RIGHT_AUX1_INPUT 0x03
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#define LEFT_AUX2_INPUT 0x04
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#define RIGHT_AUX2_INPUT 0x05
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#define LEFT_LINE_IN 0x12
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#define RIGHT_LINE_IN 0x13
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#define LEFT_LINE_OUT 0x19
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#define RIGHT_LINE_OUT 0x1B
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#define LEFT_SOURCE 0x00
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#define RIGHT_SOURCE 0x01
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#define LINE_IN 0x00
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#define AUX1_IN 0x40
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#define MIC_IN 0x80
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#define MIX_IN 0xC0
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#define LEFT_DAC 0x06
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#define RIGHT_DAC 0x07
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#define LEFT_MIC_IN 0x16
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#define RIGHT_MIC_IN 0x17
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#define CUPCTI 0x0E
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#define CLPCTI 0x0F
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#define CURCTI 0x1E
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#define CLRCTI 0x1F
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#define CLAX1I 0x02
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#define CRAX1I 0x03
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#define CLAX2I 0x04
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#define CRAX2I 0x05
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#define CLLICI 0x12
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#define CRLICI 0x13
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#define CLOAI 0x19
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#define CROAI 0x1B
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#define CLICI 0x00
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#define CRICI 0x01
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#define CLDACI 0x06
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#define CRDACI 0x07
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#define CPVFI 0x1D
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#define MAX_DMA 0x07
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#define DMA_DECREMENT 0x20
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#define AUTO_INIT 0x10
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#define DMA_READ 0x01
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#define DMA_WRITE 0x02
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#define AUTO_READ 0x03
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#define AUTO_WRITE 0x04
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#define IDMA_INV 0x0400
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#define IDMA_WIDTH_16 0x0100
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#define LDMACI 0x41 /* Index */
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#define DMA_INV 0x80
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#define DMA_IRQ_ENABLE 0x20
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#define DMA_IRQ_PENDING 0x40 /* on reads of LDMACI[6] */
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#define DMA_DATA_16 0x40 /* on writes to LDMACI[6] */
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#define DMA_WIDTH_16 0x04 /* 1=16-bit, 0=8-bit (DMA channel) */
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#define DMA_RATE 0x18 /* 00=fastest,...,11=slowest */
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#define DMA_UPLOAD 0x02 /* From LM to PC */
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#define DMA_ENABLE 0x01
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#define GUS_MODE 0x00 /* SGMI[0]=0 */
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#define ENH_MODE 0x01 /* SGMI[0]=1 */
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#define ENABLE_LFOS 0x02 /* SGMI[1] */
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#define NO_WAVETABLE 0x04 /* SGMI[2] */
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#define RAM_TEST 0x08 /* SGMI[3] */
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#define DMA_SET_MASK 0x04
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#define VOICE_STOP 0x02 /* SACI[1] */
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#define VOICE_STOPPED 0x01 /* SACI[0] */
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#define LDSALI 0x42
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#define LDSAHI 0x50
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#define LMALI 0x43
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#define LMAHI 0x44
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#define LMCFI 0x52
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#define LMCI 0x53
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#define LMFSI 0x56
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#define LDIBI 0x58
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#define LDICI 0x57
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#define LMSBAI 0x51
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#define LMRFAI 0x54
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#define LMPFAI 0x55
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#define SVCI_RD 0x8D
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#define SVCI_WR 0x0D
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#define SACI_RD 0x80
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#define SACI_WR 0x00
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#define SALI_RD 0x8B
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#define SALI_WR 0x0B
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#define SAHI_RD 0x8A
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#define SAHI_WR 0x0A
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#define SASHI_RD 0x82
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#define SASHI_WR 0x02
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#define SASLI_RD 0x83
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#define SASLI_WR 0x03
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#define SAEHI_RD 0x84
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#define SAEHI_WR 0x04
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#define SAELI_RD 0x85
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#define SAELI_WR 0x05
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#define SVRI_RD 0x86
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#define SVRI_WR 0x06
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#define SVSI_RD 0x87
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#define SVSI_WR 0x07
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#define SVEI_RD 0x88
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#define SVEI_WR 0x08
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#define SVLI_RD 0x89
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#define SVLI_WR 0x09
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#define SROI_RD 0x8C
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#define SROI_WR 0x0C
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#define SLOI_RD 0x93
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#define SLOI_WR 0x13
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#define SMSI_RD 0x95
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#define SMSI_WR 0x15
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#define SGMI_RD 0x99
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#define SGMI_WR 0x19
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#define SFCI_RD 0x81
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#define SFCI_WR 0x01
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#define SUAI_RD 0x90
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#define SUAI_WR 0x10
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#define SVII 0x8F
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#define CMODEI 0x0C /* index for CMODEI */
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#define CMONOI 0x1A
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#define CFIG3I 0x11
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#define CFIG2I 0x10
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#define CLTIMI 0x14
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#define CUTIMI 0x15
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#define CSR3I 0x18 /* Index to CSR3I (Interrupt Status) */
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#define CEXTI 0x0A /* Index to External Control Register */
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#define CFIG1I 0x09 /* Index to Codec Conf Reg 1 */
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#define CSR2I 0x0B /* Index to Codec Stat Reg 2 */
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#define CPDFI 0x08 /* Index to Play Data Format Reg */
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#define CRDFI 0x1C /* Index to Rec Data Format Reg */
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#define CLMICI 0x16 /* Index to Left Mic Input Ctrl Register */
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#define CRMICI 0x17 /* Index to Right Mic Input Ctrl Register */
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#define CLCI 0x0D /* Index to Loopback Ctrl Register */
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#define IVERI 0x5B /* Index to register IVERI */
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#define IDECI 0x5A
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#define ICMPTI 0x59
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#define CODEC_MODE1 0x00
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#define CODEC_MODE2 0x40
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#define CODEC_MODE3 0x6C /* Enhanced Mode */
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#define CODEC_STATUS1 0x01
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#define CODEC_STATUS2 0x0B /* Index to CSR2I */
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#define CODEC_STATUS3 0x18 /* Index to CSR3I */
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#define PLAYBACK 0x01 /* Enable playback path CFIG1I[0]=1*/
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#define RECORD 0x02 /* Enable Record path CFIG1I[1]=1*/
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#define TIMER_ENABLE 0x40 /* CFIG2I[6] */
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#define CODEC_MCE 0x40 /* CIDXR[6] */
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#define CALIB_IN_PROGRESS 0x20 /* CSR2I[5] */
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#define CODEC_INIT 0x80 /* CIDXR[7] */
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#define BIT16_BIG 0xC0 /* 16-bit signed, big endian */
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#define IMA_ADPCM 0xA0 /* IMA-compliant ADPCM */
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#define BIT8_ALAW 0x60 /* 8-bit A-law */
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#define BIT16_LITTLE 0x40 /* 16-bit signed, little endian */
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#define BIT8_ULAW 0x20 /* 8-bit mu-law */
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#define BIT8_LINEAR 0x00 /* 8-bit unsigned */
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#define REC_DFORMAT 0x1C
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#define PLAY_DFORMAT 0x08
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#define DMA_ACCESS 0x00
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#define PIO_ACCESS 0xC0
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#define DMA_SIMPLEX 0x04
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#define STEREO 0x10 /* CxDFI[4] */
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#define AUTOCALIB 0x08 /* CFIG1I[3] */
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#define ROM_IO 0x02 /* ROM I/O cycles - LMCI[1]=1 */
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#define DRAM_IO 0x4D /* DRAM I/O cycles - LMCI[1]=0 */
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#define AUTOI 0x01 /* LMCI[0]=1 */
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#define PLDNI 0x07
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#define ACTIVATE_DEV 0x30
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#define PWAKEI 0x03 /* Index for PWAKEI */
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#define PISOCI 0x01 /* Index for PISOCI */
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#define PSECI 0xF1 /* Index for PSECI */
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#define RANGE_IOCHK 0x31 /* PURCI or PRRCI Index */
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#define MIDI_RESET 0x03
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#define IW_DMA_RECORD 0x02
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#define IW_DMA_PLAYBACK 0x01
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#define IW_MCE 0x40
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#define IN 0
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#define OUT 1
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/* codec indirect register access */
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#define IW_WRITE_CODEC_1(reg, val) \
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do {\
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bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, (u_char)(reg));\
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bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->cdatap, (u_char)val);\
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bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, 0);\
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} while (0)\
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#define IW_READ_CODEC_1(reg, ret) \
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do {\
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bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->codec_index, (u_char)(reg));\
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ret = bus_space_read_1(sc->sc_iot, sc->codec_index_h, sc->cdatap);\
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bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, 0);\
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} while (0)\
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/* iw direct register access */
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#define IW_WRITE_DIRECT_1(reg, h, val) \
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do {\
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bus_space_write_1(sc->sc_iot, h, reg, (u_char)val);\
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} while (0)\
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#define IW_READ_DIRECT_1(reg, h, ret) \
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do {\
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ret = bus_space_read_1(sc->sc_iot, h, (u_char)reg);\
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} while (0)\
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/* general indexed regs access */
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#define IW_WRITE_GENERAL_1(reg, val) \
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do {\
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bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
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bus_space_write_1(sc->sc_iot, sc->p3xr_h, 5, (u_char)val);\
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} while (0)\
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#define IW_WRITE_GENERAL_2(reg, val) \
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do {\
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bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
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bus_space_write_2(sc->sc_iot, sc->p3xr_h, 4, (u_short)val);\
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} while (0)\
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#define IW_READ_GENERAL_1(reg, ret) \
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do{\
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bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
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ret = bus_space_read_1(sc->sc_iot, sc->p3xr_h, 5);\
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} while (0)\
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#define IW_READ_GENERAL_2(reg, ret) \
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do{\
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bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\
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ret = bus_space_read_2(sc->sc_iot, sc->p3xr_h, 4);\
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} while (0)\
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#endif /* INTERWAVEREG_H */
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