633 lines
19 KiB
C
633 lines
19 KiB
C
/* $NetBSD: arn9287.c,v 1.4 2022/09/25 18:43:32 thorpej Exp $ */
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/* $OpenBSD: ar9287.c,v 1.17 2012/06/10 21:23:36 kettenis Exp $ */
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/*-
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* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* Driver for Atheros 802.11a/g/n chipsets.
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* Routines for AR9227 and AR9287 chipsets.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: arn9287.c,v 1.4 2022/09/25 18:43:32 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/queue.h>
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#include <sys/callout.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/intr.h>
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#include <net/bpf.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_ether.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <netinet/in.h>
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#include <netinet/in_systm.h>
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#include <netinet/in_var.h>
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#include <netinet/ip.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_amrr.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/ic/athnreg.h>
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#include <dev/ic/athnvar.h>
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#include <dev/ic/arn5008reg.h>
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#include <dev/ic/arn9280reg.h>
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#include <dev/ic/arn9287reg.h>
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#include <dev/ic/arn5008.h>
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#include <dev/ic/arn9280.h>
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#include <dev/ic/arn9287.h>
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#define Static static
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Static void ar9287_get_pdadcs(struct athn_softc *,
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struct ieee80211_channel *, int, int, uint8_t, uint8_t *,
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uint8_t *);
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Static const struct ar_spur_chan *
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ar9287_get_spur_chans(struct athn_softc *, int);
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Static void ar9287_init_from_rom(struct athn_softc *,
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struct ieee80211_channel *, struct ieee80211_channel *);
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Static void ar9287_olpc_get_pdgain(struct athn_softc *,
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struct ieee80211_channel *, int, int8_t *);
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Static void ar9287_olpc_init(struct athn_softc *);
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Static void ar9287_olpc_temp_compensation(struct athn_softc *);
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Static void ar9287_set_power_calib(struct athn_softc *,
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struct ieee80211_channel *);
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Static void ar9287_set_txpower(struct athn_softc *,
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struct ieee80211_channel *, struct ieee80211_channel *);
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Static void ar9287_setup(struct athn_softc *);
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Static void ar9287_swap_rom(struct athn_softc *);
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PUBLIC int
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ar9287_attach(struct athn_softc *sc)
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{
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sc->sc_eep_base = AR9287_EEP_START_LOC;
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sc->sc_eep_size = sizeof(struct ar9287_eeprom);
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sc->sc_def_nf = AR9287_PHY_CCA_MAX_GOOD_VALUE;
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sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 11;
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sc->sc_led_pin = 8;
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sc->sc_workaround = AR9285_WA_DEFAULT;
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sc->sc_ops.setup = ar9287_setup;
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sc->sc_ops.swap_rom = ar9287_swap_rom;
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sc->sc_ops.init_from_rom = ar9287_init_from_rom;
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sc->sc_ops.set_txpower = ar9287_set_txpower;
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sc->sc_ops.set_synth = ar9280_set_synth;
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sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
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sc->sc_ops.get_spur_chans = ar9287_get_spur_chans;
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sc->sc_ops.olpc_init = ar9287_olpc_init;
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sc->sc_ops.olpc_temp_compensation = ar9287_olpc_temp_compensation;
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sc->sc_ini = &ar9287_1_1_ini;
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sc->sc_serdes = &ar9280_2_0_serdes;
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return ar5008_attach(sc);
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}
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Static void
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ar9287_setup(struct athn_softc *sc)
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{
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const struct ar9287_eeprom *eep = sc->sc_eep;
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/* Determine if open loop power control should be used. */
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if (eep->baseEepHeader.openLoopPwrCntl)
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sc->sc_flags |= ATHN_FLAG_OLPC;
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sc->sc_rx_gain = &ar9287_1_1_rx_gain;
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sc->sc_tx_gain = &ar9287_1_1_tx_gain;
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}
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Static void
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ar9287_swap_rom(struct athn_softc *sc)
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{
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struct ar9287_eeprom *eep = sc->sc_eep;
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int i;
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eep->modalHeader.antCtrlCommon =
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bswap32(eep->modalHeader.antCtrlCommon);
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for (i = 0; i < AR9287_MAX_CHAINS; i++) {
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eep->modalHeader.antCtrlChain[i] =
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bswap32(eep->modalHeader.antCtrlChain[i]);
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}
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for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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eep->modalHeader.spurChans[i].spurChan =
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bswap16(eep->modalHeader.spurChans[i].spurChan);
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}
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}
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Static const struct ar_spur_chan *
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ar9287_get_spur_chans(struct athn_softc *sc, int is2ghz)
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{
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const struct ar9287_eeprom *eep = sc->sc_eep;
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KASSERT(is2ghz);
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return eep->modalHeader.spurChans;
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}
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Static void
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ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
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struct ieee80211_channel *extc)
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{
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const struct ar9287_eeprom *eep = sc->sc_eep;
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const struct ar9287_modal_eep_header *modal = &eep->modalHeader;
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uint32_t reg, offset;
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int i;
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AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
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for (i = 0; i < AR9287_MAX_CHAINS; i++) {
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offset = i * 0x1000;
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AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
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modal->antCtrlChain[i]);
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reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
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reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
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modal->iqCalICh[i]);
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reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
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modal->iqCalQCh[i]);
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AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
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reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
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reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
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modal->bswMargin[i]);
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reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
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modal->bswAtten[i]);
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AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
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reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
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reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
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modal->rxTxMarginCh[i]);
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reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
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modal->txRxAttenCh[i]);
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AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
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}
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reg = AR_READ(sc, AR_PHY_SETTLING);
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#ifndef IEEE80211_NO_HT
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if (extc != NULL)
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reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
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else
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#endif
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reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
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AR_WRITE(sc, AR_PHY_SETTLING, reg);
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reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
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reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
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AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
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reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
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reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
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reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
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reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
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AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
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reg = AR_READ(sc, AR_PHY_RF_CTL3);
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reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
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AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
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reg = AR_READ(sc, AR_PHY_CCA(0));
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reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
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AR_WRITE(sc, AR_PHY_CCA(0), reg);
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reg = AR_READ(sc, AR_PHY_EXT_CCA0);
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reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
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AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
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reg = AR_READ(sc, AR9287_AN_RF2G3_CH0);
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reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
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reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
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reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
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reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
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reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
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reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
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AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg);
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AR_WRITE_BARRIER(sc);
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DELAY(100);
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reg = AR_READ(sc, AR9287_AN_RF2G3_CH1);
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reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
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reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
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reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
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reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
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reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
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reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
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AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg);
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AR_WRITE_BARRIER(sc);
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DELAY(100);
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reg = AR_READ(sc, AR_PHY_RF_CTL2);
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reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart);
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reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
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AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
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reg = AR_READ(sc, AR9287_AN_TOP2);
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reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
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AR_WRITE(sc, AR9287_AN_TOP2, reg);
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AR_WRITE_BARRIER(sc);
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DELAY(100);
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}
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Static void
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ar9287_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
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int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries,
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uint8_t *pdadcs)
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{
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const struct ar9287_eeprom *eep = sc->sc_eep;
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const struct ar9287_cal_data_per_freq *pierdata;
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const uint8_t *pierfreq;
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struct athn_pier lopier, hipier;
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int16_t delta;
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uint8_t fbin;
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int i, lo, hi, npiers;
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pierfreq = eep->calFreqPier2G;
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pierdata = (const struct ar9287_cal_data_per_freq *)
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eep->calPierData2G[chain];
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npiers = AR9287_NUM_2G_CAL_PIERS;
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/* Find channel in ROM pier table. */
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fbin = athn_chan2fbin(c);
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athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
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lopier.fbin = pierfreq[lo];
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hipier.fbin = pierfreq[hi];
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for (i = 0; i < nxpdgains; i++) {
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lopier.pwr[i] = pierdata[lo].pwrPdg[i];
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lopier.vpd[i] = pierdata[lo].vpdPdg[i];
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hipier.pwr[i] = pierdata[lo].pwrPdg[i];
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hipier.vpd[i] = pierdata[lo].vpdPdg[i];
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}
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ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
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AR9287_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
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delta = (eep->baseEepHeader.pwrTableOffset -
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AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */
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if (delta != 0) {
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/* Shift the PDADC table to start at the new offset. */
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/* XXX Our padding value differs from Linux. */
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for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
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pdadcs[i] = pdadcs[MIN(i + delta,
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AR_NUM_PDADC_VALUES - 1)];
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}
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}
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Static void
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ar9287_olpc_get_pdgain(struct athn_softc *sc, struct ieee80211_channel *c,
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int chain, int8_t *pwr)
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{
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const struct ar9287_eeprom *eep = sc->sc_eep;
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const struct ar_cal_data_per_freq_olpc *pierdata;
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const uint8_t *pierfreq;
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uint8_t fbin;
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int lo, hi, npiers;
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pierfreq = eep->calFreqPier2G;
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pierdata = (const struct ar_cal_data_per_freq_olpc *)
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eep->calPierData2G[chain];
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npiers = AR9287_NUM_2G_CAL_PIERS;
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/* Find channel in ROM pier table. */
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fbin = athn_chan2fbin(c);
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athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
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#if 0
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*pwr = athn_interpolate(fbin,
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pierfreq[lo], pierdata[lo].pwrPdg[0][0],
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pierfreq[hi], pierdata[hi].pwrPdg[0][0]);
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#else
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*pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;
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#endif
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}
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Static void
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ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
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{
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const struct ar9287_eeprom *eep = sc->sc_eep;
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uint8_t boundaries[AR_PD_GAINS_IN_MASK];
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uint8_t pdadcs[AR_NUM_PDADC_VALUES];
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uint8_t xpdgains[AR9287_NUM_PD_GAINS];
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int8_t txpower;
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uint8_t overlap;
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uint32_t reg, offset;
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int i, j, nxpdgains;
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if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) {
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overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
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AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
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}
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else
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overlap = eep->modalHeader.pdGainOverlap;
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if (sc->sc_flags & ATHN_FLAG_OLPC) {
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/* XXX not here. */
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sc->sc_pdadc =
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((const struct ar_cal_data_per_freq_olpc *)
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eep->calPierData2G[0])->vpdPdg[0][0];
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}
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nxpdgains = 0;
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memset(xpdgains, 0, sizeof(xpdgains));
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for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
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if (nxpdgains >= AR9287_NUM_PD_GAINS)
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break; /* Can't happen. */
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if (eep->modalHeader.xpdGain & (1 << i))
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xpdgains[nxpdgains++] = i;
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}
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reg = AR_READ(sc, AR_PHY_TPCRG1);
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reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
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reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
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reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
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AR_WRITE(sc, AR_PHY_TPCRG1, reg);
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AR_WRITE_BARRIER(sc);
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for (i = 0; i < AR9287_MAX_CHAINS; i++) {
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if (!(sc->sc_txchainmask & (1 << i)))
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continue;
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offset = i * 0x1000;
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if (sc->sc_flags & ATHN_FLAG_OLPC) {
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ar9287_olpc_get_pdgain(sc, c, i, &txpower);
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reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
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reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
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AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
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reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
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reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
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AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
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/* NB: txpower is in half dB. */
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reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset);
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reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);
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AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg);
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AR_WRITE_BARRIER(sc);
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continue; /* That's it for open loop mode. */
|
|
}
|
|
|
|
/* Closed loop power control. */
|
|
ar9287_get_pdadcs(sc, c, i, nxpdgains, overlap,
|
|
boundaries, pdadcs);
|
|
|
|
/* Write boundaries. */
|
|
if (i == 0) {
|
|
reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
|
|
overlap);
|
|
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
|
|
boundaries[0]);
|
|
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
|
|
boundaries[1]);
|
|
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
|
|
boundaries[2]);
|
|
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
|
|
boundaries[3]);
|
|
AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
|
|
}
|
|
/* Write PDADC values. */
|
|
for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) {
|
|
AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
|
|
pdadcs[j + 0] << 0 |
|
|
pdadcs[j + 1] << 8 |
|
|
pdadcs[j + 2] << 16 |
|
|
pdadcs[j + 3] << 24);
|
|
}
|
|
AR_WRITE_BARRIER(sc);
|
|
}
|
|
}
|
|
|
|
Static void
|
|
ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
|
|
struct ieee80211_channel *extc)
|
|
{
|
|
const struct ar9287_eeprom *eep = sc->sc_eep;
|
|
#ifdef notyet
|
|
const struct ar9287_modal_eep_header *modal = &eep->modalHeader;
|
|
#endif
|
|
uint8_t tpow_cck[4], tpow_ofdm[4];
|
|
#ifndef IEEE80211_NO_HT
|
|
uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
|
|
uint8_t tpow_ht20[8], tpow_ht40[8];
|
|
uint8_t ht40inc;
|
|
#endif
|
|
int16_t pwr = 0, power[ATHN_POWER_COUNT];
|
|
int i;
|
|
|
|
ar9287_set_power_calib(sc, c);
|
|
|
|
#ifdef notyet
|
|
/* Compute transmit power reduction due to antenna gain. */
|
|
uint16_t max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]);
|
|
/* XXX */
|
|
#endif
|
|
|
|
/*
|
|
* Reduce scaled power by number of active chains to get per-chain
|
|
* transmit power level.
|
|
*/
|
|
if (sc->sc_ntxchains == 2)
|
|
pwr -= AR_PWR_DECREASE_FOR_2_CHAIN;
|
|
if (pwr < 0)
|
|
pwr = 0;
|
|
|
|
/* Get CCK target powers. */
|
|
ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
|
|
AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
|
|
|
|
/* Get OFDM target powers. */
|
|
ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
|
|
AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
|
|
|
|
#ifndef IEEE80211_NO_HT
|
|
/* Get HT-20 target powers. */
|
|
ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
|
|
AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20);
|
|
|
|
if (extc != NULL) {
|
|
/* Get HT-40 target powers. */
|
|
ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
|
|
eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS,
|
|
tpow_ht40);
|
|
|
|
/* Get secondary channel CCK target powers. */
|
|
ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
|
|
eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS,
|
|
tpow_cck_ext);
|
|
|
|
/* Get secondary channel OFDM target powers. */
|
|
ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
|
|
eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS,
|
|
tpow_ofdm_ext);
|
|
}
|
|
#endif
|
|
|
|
memset(power, 0, sizeof(power));
|
|
/* Shuffle target powers accross transmit rates. */
|
|
power[ATHN_POWER_OFDM6 ] =
|
|
power[ATHN_POWER_OFDM9 ] =
|
|
power[ATHN_POWER_OFDM12 ] =
|
|
power[ATHN_POWER_OFDM18 ] =
|
|
power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0];
|
|
power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1];
|
|
power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2];
|
|
power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3];
|
|
power[ATHN_POWER_XR ] = tpow_ofdm[0];
|
|
power[ATHN_POWER_CCK1_LP ] = tpow_cck[0];
|
|
power[ATHN_POWER_CCK2_LP ] =
|
|
power[ATHN_POWER_CCK2_SP ] = tpow_cck[1];
|
|
power[ATHN_POWER_CCK55_LP] =
|
|
power[ATHN_POWER_CCK55_SP] = tpow_cck[2];
|
|
power[ATHN_POWER_CCK11_LP] =
|
|
power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
|
|
#ifndef IEEE80211_NO_HT
|
|
for (i = 0; i < nitems(tpow_ht20); i++)
|
|
power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
|
|
if (extc != NULL) {
|
|
/* Correct PAR difference between HT40 and HT20/Legacy. */
|
|
if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
|
|
ht40inc = modal->ht40PowerIncForPdadc;
|
|
else
|
|
ht40inc = AR_HT40_POWER_INC_FOR_PDADC;
|
|
for (i = 0; i < nitems(tpow_ht40); i++)
|
|
power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc;
|
|
power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0];
|
|
power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0];
|
|
power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];
|
|
if (IEEE80211_IS_CHAN_2GHZ(c))
|
|
power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0];
|
|
}
|
|
#endif
|
|
|
|
for (i = 0; i < ATHN_POWER_COUNT; i++) {
|
|
power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */
|
|
if (power[i] > AR_MAX_RATE_POWER)
|
|
power[i] = AR_MAX_RATE_POWER;
|
|
}
|
|
/* Commit transmit power values to hardware. */
|
|
ar5008_write_txpower(sc, power);
|
|
}
|
|
|
|
Static void
|
|
ar9287_olpc_init(struct athn_softc *sc)
|
|
{
|
|
uint32_t reg;
|
|
|
|
AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
|
|
|
|
reg = AR_READ(sc, AR9287_AN_TXPC0);
|
|
reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,
|
|
AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
|
|
AR_WRITE(sc, AR9287_AN_TXPC0, reg);
|
|
AR_WRITE_BARRIER(sc);
|
|
DELAY(100);
|
|
}
|
|
|
|
Static void
|
|
ar9287_olpc_temp_compensation(struct athn_softc *sc)
|
|
{
|
|
const struct ar9287_eeprom *eep = sc->sc_eep;
|
|
int8_t pdadc, slope, tcomp;
|
|
uint32_t reg;
|
|
|
|
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
|
|
pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
|
|
DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc);
|
|
|
|
if (sc->sc_pdadc == 0 || pdadc == 0)
|
|
return; /* No frames transmitted yet. */
|
|
|
|
/* Compute Tx gain temperature compensation. */
|
|
if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
|
|
slope = eep->baseEepHeader.tempSensSlope;
|
|
else
|
|
slope = 0;
|
|
if (slope != 0) /* Prevents division by zero. */
|
|
tcomp = ((pdadc - sc->sc_pdadc) * 4) / slope;
|
|
else
|
|
tcomp = 0;
|
|
DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp);
|
|
|
|
/* Write compensation value for both Tx chains. */
|
|
reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11);
|
|
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
|
|
AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg);
|
|
|
|
reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11);
|
|
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
|
|
AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg);
|
|
AR_WRITE_BARRIER(sc);
|
|
}
|
|
|
|
PUBLIC void
|
|
ar9287_1_3_enable_async_fifo(struct athn_softc *sc)
|
|
{
|
|
|
|
/* Enable ASYNC FIFO. */
|
|
AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
|
|
AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
|
|
AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
|
|
AR_CLRBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
|
|
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
|
|
AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
|
|
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
|
|
AR_WRITE_BARRIER(sc);
|
|
}
|
|
|
|
PUBLIC void
|
|
ar9287_1_3_setup_async_fifo(struct athn_softc *sc)
|
|
{
|
|
uint32_t reg;
|
|
|
|
/*
|
|
* MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is
|
|
* enabled, so the following counters have to be changed.
|
|
*/
|
|
AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
|
|
AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
|
|
AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
|
|
|
|
AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
|
|
AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
|
|
|
|
AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER,
|
|
AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
|
|
|
|
reg = AR_READ(sc, AR_AHB_MODE);
|
|
reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
|
|
AR_WRITE(sc, AR_AHB_MODE, reg);
|
|
|
|
AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
|
|
AR_WRITE_BARRIER(sc);
|
|
}
|