213 lines
6.0 KiB
C
213 lines
6.0 KiB
C
/* $NetBSD: if_tr_mca.c,v 1.1 2000/05/11 15:42:04 jdolecek Exp $ */
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/*_
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* Copyright (c) 1998, 1999 Gregory McGarry.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Gregory McGarry <g.mcgarry@qut.edu.au>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/socket.h>
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#include <sys/device.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/mca/mcareg.h>
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#include <dev/mca/mcavar.h>
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#include <dev/mca/mcadevs.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#include <dev/ic/tropicreg.h>
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#include <dev/ic/tropicvar.h>
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#ifdef DEBUG
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#define DPRINTF(x) printf x
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#else
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#define DPRINTF(x)
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#endif
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#define TR_PRI_IOADDR 0x0a20
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#define TR_ALT_IOADDR 0x0a24
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#define TR_PIOSIZE 4
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#define TR_MMIOSIZE 8192
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#define TR_MBPS_4 0
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#define TR_MBPS_16 1
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int tr_mca_probe __P((struct device *, struct cfdata *, void *));
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void tr_mca_attach __P((struct device *, struct device *, void *));
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struct cfattach tr_mca_ca = {
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sizeof(struct tr_softc), tr_mca_probe, tr_mca_attach
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};
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int
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tr_mca_probe(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct mca_attach_args *ma = aux;
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switch (ma->ma_id) {
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case MCA_PRODUCT_ITR:
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return 1;
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}
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return 0;
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}
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void
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tr_mca_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct tr_softc *sc = (void *) self;
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struct mca_attach_args *ma = aux;
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bus_space_handle_t pioh, mmioh, sramh;
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int iobase, irq, sram_size, sram_addr, rom_addr;
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int pos2, pos3, pos4, pos5;
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pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2);
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pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3);
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pos4 = mca_conf_read(ma->ma_mc, ma->ma_slot, 4);
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pos5 = mca_conf_read(ma->ma_mc, ma->ma_slot, 5);
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/*
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* POS register 2: (adf pos0)
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*
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* 7 6 5 4 3 2 1 0
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* \___________/ \__ enable: 0=adapter disabled, 1=adapter enabled
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* \__________ RAM addr: pos2&0xfe
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*
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* POS register 3: (adf pos1)
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*
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* 7 6 5 4 3 2 1 0
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* | \___/ | | | \__ port address: 1=0x0a24-0x0a27, 0=0x0a20-0x0a23
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* | | \ / \____ speed: 0=4Mbps, 1=16Mbps
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* | | \_______ RAM size: 00=8kb, 01=16kb, 10=32kb, 11=64kb
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* | \____________ reserved: 010
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* \________________ irq component: 0=2, 1=3 (see also pos4)
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*
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* POS register 4: (adf pos2)
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*
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* 7 6 5 4 3 2 1 0
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* \___________/ \__ interrupt controller: 0=1st, 1=2nd
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* \__________ ROM address: pos4&0xfe
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*
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* POS register 5: (adf pos3)
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*
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* 7 6 5 4 3 2 1 0
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* | | \_____/
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* | | \_____ reserved: 0x0
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* | \__________ autosense: 0=off, 1=on
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* \____________ boot rom: 0=enabled, 1=disabled
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*/
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if (pos3 & 0x01)
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iobase = TR_ALT_IOADDR;
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else
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iobase = TR_PRI_IOADDR;
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irq = 2 + (pos3 >> 7) + ((pos4 & 0x01) << 3);
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if (irq == 2)
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irq = 9;
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sram_size = 8 << (((pos3 & 0x0c) >> 2) + 10);
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sram_addr = (pos2 & 0xfe) << 12;
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rom_addr = (pos4 & 0xfe) << 12;
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/* map the pio registers */
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if (bus_space_map(ma->ma_iot, iobase, TR_PIOSIZE, 0, &pioh)) {
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printf("%s: unable to map PIO space\n", sc->sc_dev.dv_xname);
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return;
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}
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/* map the mmio registers */
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if (bus_space_map(ma->ma_memt, rom_addr, TR_MMIOSIZE, 0, &mmioh)) {
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printf("%s: unable to map MMIO space\n", sc->sc_dev.dv_xname);
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return;
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}
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/* map the sram space */
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if (bus_space_map(ma->ma_memt, sram_addr, sram_size, 0, &sramh)) {
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printf("%s: unable to map SRAM space\n", sc->sc_dev.dv_xname);
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return;
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}
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sc->sc_piot = ma->ma_iot;
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sc->sc_pioh = pioh;
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sc->sc_memt = ma->ma_memt;
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sc->sc_mmioh = mmioh;
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sc->sc_sramh = sramh;
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/* set ACA offset */
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sc->sc_aca = TR_ACA_OFFSET;
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sc->sc_memwinsz = sram_size;
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sc->sc_maddr = sram_addr;
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/*
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* Determine total RAM on adapter and decide how much to use.
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* XXX Since we don't use RAM paging, use sc_memwinsz for now.
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*/
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sc->sc_memsize = sc->sc_memwinsz;
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sc->sc_memreserved = 0;
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if (tr_reset(sc) != 0)
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return;
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/* XXX not implemented (yet) */
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sc->sc_mediastatus = NULL;
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sc->sc_mediachange = NULL;
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/* do generic attach */
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if (tr_attach(sc) != 0)
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return;
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/* establish interrupt handler */
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sc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_NET, tr_intr, sc);
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if (sc->sc_ih == NULL)
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printf("%s: couldn't establish interrupt handler\n",
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sc->sc_dev.dv_xname);
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else
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printf("%s: interrupting at irq %d\n", sc->sc_dev.dv_xname, irq);
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}
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