956 lines
24 KiB
C
956 lines
24 KiB
C
/* $NetBSD: tx3912video.c,v 1.14 2000/05/12 18:09:55 uch Exp $ */
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/*-
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* Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#undef TX3912VIDEO_DEBUG
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#include "opt_tx39_debug.h"
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#include "hpcfb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/ioctl.h>
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#include <sys/buf.h>
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#include <vm/vm.h>
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#include <machine/bus.h>
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#include <machine/bootinfo.h>
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#include <hpcmips/tx/tx39var.h>
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#include <hpcmips/tx/tx3912videovar.h>
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#include <hpcmips/tx/tx3912videoreg.h>
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/* CLUT */
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#include <dev/wscons/wsdisplayvar.h>
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#include <dev/rasops/rasops.h>
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#include <arch/hpcmips/dev/video_subr.h>
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#include <dev/wscons/wsconsio.h>
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#include <arch/hpcmips/dev/hpcfbvar.h>
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#include <arch/hpcmips/dev/hpcfbio.h>
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static struct tx3912video_chip {
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tx_chipset_tag_t vc_tc;
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paddr_t vc_fbaddr;
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size_t vc_fbsize;
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int vc_fbdepth;
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int vc_fbwidth;
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int vc_fbheight;
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void (*vc_drawline) __P((int, int, int, int)); /* for debug */
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void (*vc_drawdot) __P((int, int)); /* for debug */
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} tx3912video_chip;
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struct tx3912video_softc {
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struct device sc_dev;
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struct hpcfb_fbconf sc_fbconf;
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struct hpcfb_dspconf sc_dspconf;
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struct tx3912video_chip *sc_chip;
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};
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void tx3912video_framebuffer_init __P((struct tx3912video_chip *));
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int tx3912video_framebuffer_alloc __P((struct tx3912video_chip *, paddr_t,
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paddr_t *));
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void tx3912video_reset __P((struct tx3912video_chip *));
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void tx3912video_resolution_init __P((struct tx3912video_chip *));
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int tx3912video_match __P((struct device *, struct cfdata *, void *));
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void tx3912video_attach __P((struct device *, struct device *, void *));
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int tx3912video_print __P((void *, const char *));
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void tx3912video_hpcfbinit __P((struct tx3912video_softc *));
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int tx3912video_ioctl __P((void *, u_long, caddr_t, int, struct proc *));
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int tx3912video_mmap __P((void *, off_t, int));
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void tx3912video_clut_init __P((struct tx3912video_softc *));
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void tx3912video_clut_install __P((void *, struct rasops_info *));
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void tx3912video_clut_get __P((struct tx3912video_softc *,
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u_int32_t *, int, int));
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static int __get_color8 __P((int));
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static int __get_color4 __P((int));
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struct cfattach tx3912video_ca = {
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sizeof(struct tx3912video_softc), tx3912video_match,
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tx3912video_attach
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};
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struct hpcfb_accessops tx3912video_ha = {
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tx3912video_ioctl, tx3912video_mmap, 0, 0, 0, 0,
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tx3912video_clut_install
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};
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void __tx3912video_attach_drawfunc __P((struct tx3912video_chip*));
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int
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tx3912video_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return (1);
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}
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void
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tx3912video_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct tx3912video_softc *sc = (void *)self;
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struct tx3912video_chip *chip;
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const char *depth_print[] = {
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[TX3912_VIDEOCTRL1_BITSEL_MONOCHROME] = "monochrome",
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[TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE] = "2bit greyscale",
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[TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE] = "4bit greyscale",
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[TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR] = "8bit color"
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};
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struct hpcfb_attach_args ha;
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tx_chipset_tag_t tc;
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txreg_t val;
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int console = (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) ? 0 : 1;
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sc->sc_chip = chip = &tx3912video_chip;
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/* print video module information */
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printf(": %s, frame buffer 0x%08x-0x%08x\n",
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depth_print[(ffs(chip->vc_fbdepth) - 1) & 0x3],
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(unsigned)chip->vc_fbaddr,
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(unsigned)(chip->vc_fbaddr + chip->vc_fbsize));
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/* don't inverse VDAT[3:0] signal */
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tc = chip->vc_tc;
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val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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val &= ~TX3912_VIDEOCTRL1_INVVID;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
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/* install default CLUT */
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tx3912video_clut_init(sc);
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/* if serial console, power off video module */
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#ifndef TX3912VIDEO_DEBUG
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if (!console) {
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printf("%s: power off\n", sc->sc_dev.dv_xname);
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val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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val &= ~(TX3912_VIDEOCTRL1_DISPON |
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TX3912_VIDEOCTRL1_ENVID);
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
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}
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#endif /* TX3912VIDEO_DEBUG */
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#ifdef TX3912VIDEO_DEBUG
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/* attach debug draw routine (debugging use) */
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__tx3912video_attach_drawfunc(sc->sc_chip);
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#endif
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/* Attach frame buffer device */
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tx3912video_hpcfbinit(sc);
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if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) {
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panic("tx3912video_attach: can't init fb console");
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}
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ha.ha_console = console;
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ha.ha_accessops = &tx3912video_ha;
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ha.ha_accessctx = sc;
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ha.ha_curfbconf = 0;
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ha.ha_nfbconf = 1;
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ha.ha_fbconflist = &sc->sc_fbconf;
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ha.ha_curdspconf = 0;
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ha.ha_ndspconf = 1;
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ha.ha_dspconflist = &sc->sc_dspconf;
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config_found(self, &ha, hpcfbprint);
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}
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void
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tx3912video_hpcfbinit(sc)
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struct tx3912video_softc *sc;
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{
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struct tx3912video_chip *chip = sc->sc_chip;
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struct hpcfb_fbconf *fb = &sc->sc_fbconf;
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vaddr_t fbvaddr = (vaddr_t)MIPS_PHYS_TO_KSEG1(chip->vc_fbaddr);
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memset(fb, 0, sizeof(struct hpcfb_fbconf));
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fb->hf_conf_index = 0; /* configuration index */
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fb->hf_nconfs = 1; /* how many configurations */
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strncpy(fb->hf_name, "TX3912 built-in video", HPCFB_MAXNAMELEN);
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/* frame buffer name */
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strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN);
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/* configuration name */
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fb->hf_height = chip->vc_fbheight;
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fb->hf_width = chip->vc_fbwidth;
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fb->hf_baseaddr = mips_ptob(mips_btop(fbvaddr));
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fb->hf_offset = (u_long)fbvaddr - fb->hf_baseaddr;
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/* frame buffer start offset */
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fb->hf_bytes_per_line = (chip->vc_fbwidth * chip->vc_fbdepth)
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/ NBBY;
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fb->hf_nplanes = 1;
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fb->hf_bytes_per_plane = chip->vc_fbheight * fb->hf_bytes_per_line;
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fb->hf_access_flags |= HPCFB_ACCESS_BYTE;
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fb->hf_access_flags |= HPCFB_ACCESS_WORD;
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fb->hf_access_flags |= HPCFB_ACCESS_DWORD;
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switch (chip->vc_fbdepth) {
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default:
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panic("tx3912video_hpcfbinit: not supported color depth\n");
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/* NOTREACHED */
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case 2:
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fb->hf_class = HPCFB_CLASS_GRAYSCALE;
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fb->hf_access_flags |= HPCFB_ACCESS_STATIC;
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fb->hf_pack_width = 8;
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fb->hf_pixels_per_pack = 4;
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fb->hf_pixel_width = 2;
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fb->hf_class_data_length = sizeof(struct hf_gray_tag);
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/* reserved for future use */
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fb->hf_u.hf_gray.hf_flags = 0;
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break;
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case 8:
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fb->hf_class = HPCFB_CLASS_INDEXCOLOR;
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fb->hf_access_flags |= HPCFB_ACCESS_STATIC;
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fb->hf_pack_width = 8;
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fb->hf_pixels_per_pack = 1;
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fb->hf_pixel_width = 8;
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fb->hf_class_data_length = sizeof(struct hf_indexed_tag);
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/* reserved for future use */
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fb->hf_u.hf_indexed.hf_flags = 0;
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break;
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}
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}
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int
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tx3912video_init(fb_start, fb_end)
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paddr_t fb_start, *fb_end;
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{
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struct tx3912video_chip *chip = &tx3912video_chip;
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tx_chipset_tag_t tc;
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txreg_t reg;
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int fbdepth;
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int error;
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chip->vc_tc = tc = tx_conf_get_tag();
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg));
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switch (fbdepth) {
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case 2:
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bootinfo->fb_type = BIFB_D2_M2L_0;
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break;
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case 4:
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/* XXX should implement rasops4.c */
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fbdepth = 2;
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bootinfo->fb_type = BIFB_D2_M2L_0;
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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TX3912_VIDEOCTRL1_BITSEL_CLR(reg);
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reg = TX3912_VIDEOCTRL1_BITSEL_SET(
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reg, TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE);
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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break;
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case 8:
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bootinfo->fb_type = BIFB_D8_FF;
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break;
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}
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tx3912video_chip.vc_fbdepth = fbdepth;
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tx3912video_chip.vc_fbwidth = bootinfo->fb_width;
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tx3912video_chip.vc_fbheight= bootinfo->fb_height;
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/* Allocate framebuffer area */
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error = tx3912video_framebuffer_alloc(chip, fb_start, fb_end);
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if (error != 0)
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return (1);
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#if notyet
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tx3912video_resolution_init(chip);
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#else
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/* Use Windows CE setting. */
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#endif
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/* Set DMA transfer address to VID module */
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tx3912video_framebuffer_init(chip);
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/* Syncronize framebuffer addr to frame signal */
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tx3912video_reset(chip);
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bootinfo->fb_line_bytes = (chip->vc_fbwidth * fbdepth) / NBBY;
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bootinfo->fb_addr = (void *)MIPS_PHYS_TO_KSEG1(chip->vc_fbaddr);
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return (0);
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}
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int
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tx3912video_framebuffer_alloc(chip, fb_start, fb_end)
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struct tx3912video_chip *chip;
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paddr_t fb_start, *fb_end; /* buffer allocation hint */
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{
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struct extent_fixed ex_fixed[10];
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struct extent *ex;
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u_long addr, size;
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int error;
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/* calcurate frame buffer size */
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size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) /
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NBBY;
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/* extent V-RAM region */
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ex = extent_create("Frame buffer address", fb_start, *fb_end,
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0, (caddr_t)ex_fixed, sizeof ex_fixed,
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EX_NOWAIT);
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if (ex == 0)
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return (1);
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/* Allocate V-RAM area */
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error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1,
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size, TX3912_FRAMEBUFFER_ALIGNMENT,
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TX3912_FRAMEBUFFER_BOUNDARY,
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EX_FAST|EX_NOWAIT, &addr);
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extent_destroy(ex);
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if (error != 0) {
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return (1);
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}
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chip->vc_fbaddr = addr;
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chip->vc_fbsize = size;
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*fb_end = addr + size;
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return (0);
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}
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void
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tx3912video_framebuffer_init(chip)
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struct tx3912video_chip *chip;
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{
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u_int32_t fb_addr, fb_size, vaddr, bank, base;
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txreg_t reg;
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tx_chipset_tag_t tc = chip->vc_tc;
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fb_addr = chip->vc_fbaddr;
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fb_size = chip->vc_fbsize;
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/* XXX currently I don't set DFVAL, so force DF signal toggled on
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* XXX each frame. */
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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reg &= ~TX3912_VIDEOCTRL1_DFMODE;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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/* Set DMA transfer start and end address */
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bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr);
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base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr);
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reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank);
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/* Upper address counter */
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reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base);
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tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg);
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/* Lower address counter */
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base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size);
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reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base);
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/* Set DF-signal rate */
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reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/
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/* Set VIDDONE signal delay after FRAME signal */
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/* XXX not yet*/
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tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg);
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/* Clear frame buffer */
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vaddr = MIPS_PHYS_TO_KSEG1(fb_addr);
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memset((void*)vaddr, 0, fb_size);
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}
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void
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tx3912video_resolution_init(chip)
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struct tx3912video_chip *chip;
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{
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int h, v, split, bit8, horzval, lineval;
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tx_chipset_tag_t tc = chip->vc_tc;
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txreg_t reg;
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u_int32_t val;
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h = chip->vc_fbwidth;
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v = chip->vc_fbheight;
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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split = reg & TX3912_VIDEOCTRL1_DISPSPLIT;
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bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) ==
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TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR);
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val = TX3912_VIDEOCTRL1_BITSEL(reg);
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if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) &&
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!split) {
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/* (LCD horizontal pixels / 8bit) * RGB - 1 */
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horzval = (h / 8) * 3 - 1;
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} else {
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horzval = h / 4 - 1;
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}
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lineval = (split ? v / 2 : v) - 1;
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/* Video rate */
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/* XXX
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* probably This value should be determined from DFINT and LCDINT
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*/
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reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1);
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/* Horizontal size of LCD */
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reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval);
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/* # of lines for the LCD */
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reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval);
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tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg);
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}
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void
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tx3912video_reset(chip)
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struct tx3912video_chip *chip;
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{
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tx_chipset_tag_t tc = chip->vc_tc;
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txreg_t reg;
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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/* Disable video logic at end of this frame */
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reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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/* Wait for end of frame */
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delay(30 * 1000);
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/* Make sure to disable video logic */
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reg &= ~TX3912_VIDEOCTRL1_ENVID;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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delay(1000);
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/* Enable video logic again */
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reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME;
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reg |= TX3912_VIDEOCTRL1_ENVID;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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delay(1000);
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}
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int
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tx3912video_ioctl(v, cmd, data, flag, p)
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void *v;
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u_long cmd;
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caddr_t data;
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int flag;
|
|
struct proc *p;
|
|
{
|
|
struct tx3912video_softc *sc = (struct tx3912video_softc *)v;
|
|
struct hpcfb_fbconf *fbconf;
|
|
struct hpcfb_dspconf *dspconf;
|
|
struct wsdisplay_cmap *cmap;
|
|
u_int8_t *r, *g, *b;
|
|
u_int32_t *rgb;
|
|
int idx, cnt, error;
|
|
|
|
switch (cmd) {
|
|
case WSDISPLAYIO_GETCMAP:
|
|
cmap = (struct wsdisplay_cmap*)data;
|
|
cnt = cmap->count;
|
|
idx = cmap->index;
|
|
|
|
if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR ||
|
|
sc->sc_fbconf.hf_pack_width != 8 ||
|
|
!LEGAL_CLUT_INDEX(idx) ||
|
|
!LEGAL_CLUT_INDEX(idx + cnt -1)) {
|
|
return (EINVAL);
|
|
}
|
|
|
|
if (!uvm_useracc(cmap->red, cnt, B_WRITE) ||
|
|
!uvm_useracc(cmap->green, cnt, B_WRITE) ||
|
|
!uvm_useracc(cmap->blue, cnt, B_WRITE)) {
|
|
return (EFAULT);
|
|
}
|
|
|
|
error = cmap_work_alloc(&r, &g, &b, &rgb, cnt);
|
|
if (error != 0) {
|
|
cmap_work_free(r, g, b, rgb);
|
|
return (ENOMEM);
|
|
}
|
|
tx3912video_clut_get(sc, rgb, idx, cnt);
|
|
rgb24_decompose(rgb, r, g, b, cnt);
|
|
|
|
copyout(r, cmap->red, cnt);
|
|
copyout(g, cmap->green,cnt);
|
|
copyout(b, cmap->blue, cnt);
|
|
|
|
cmap_work_free(r, g, b, rgb);
|
|
|
|
return (0);
|
|
|
|
case WSDISPLAYIO_PUTCMAP:
|
|
/*
|
|
* TX3912 can't change CLUT index. R:G:B = 3:3:2
|
|
*/
|
|
return (0);
|
|
|
|
case HPCFBIO_GCONF:
|
|
fbconf = (struct hpcfb_fbconf *)data;
|
|
if (fbconf->hf_conf_index != 0 &&
|
|
fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) {
|
|
return (EINVAL);
|
|
}
|
|
*fbconf = sc->sc_fbconf; /* structure assignment */
|
|
return (0);
|
|
|
|
case HPCFBIO_SCONF:
|
|
fbconf = (struct hpcfb_fbconf *)data;
|
|
if (fbconf->hf_conf_index != 0 &&
|
|
fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) {
|
|
return (EINVAL);
|
|
}
|
|
/*
|
|
* nothing to do because we have only one configration
|
|
*/
|
|
return (0);
|
|
|
|
case HPCFBIO_GDSPCONF:
|
|
dspconf = (struct hpcfb_dspconf *)data;
|
|
if ((dspconf->hd_unit_index != 0 &&
|
|
dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) ||
|
|
(dspconf->hd_conf_index != 0 &&
|
|
dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) {
|
|
return (EINVAL);
|
|
}
|
|
*dspconf = sc->sc_dspconf; /* structure assignment */
|
|
return (0);
|
|
|
|
case HPCFBIO_SDSPCONF:
|
|
dspconf = (struct hpcfb_dspconf *)data;
|
|
if ((dspconf->hd_unit_index != 0 &&
|
|
dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) ||
|
|
(dspconf->hd_conf_index != 0 &&
|
|
dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) {
|
|
return (EINVAL);
|
|
}
|
|
/*
|
|
* nothing to do
|
|
* because we have only one unit and one configration
|
|
*/
|
|
return (0);
|
|
|
|
case HPCFBIO_GOP:
|
|
case HPCFBIO_SOP:
|
|
/* XXX not implemented yet */
|
|
return (EINVAL);
|
|
}
|
|
|
|
return (ENOTTY);
|
|
}
|
|
|
|
int
|
|
tx3912video_mmap(ctx, offset, prot)
|
|
void *ctx;
|
|
off_t offset;
|
|
int prot;
|
|
{
|
|
struct tx3912video_softc *sc = (struct tx3912video_softc *)ctx;
|
|
|
|
if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane +
|
|
sc->sc_fbconf.hf_offset) < offset) {
|
|
return (-1);
|
|
}
|
|
|
|
return (mips_btop(sc->sc_chip->vc_fbaddr + offset));
|
|
}
|
|
|
|
/*
|
|
* CLUT staff
|
|
*/
|
|
static const struct {
|
|
int mul, div;
|
|
} dither_list [] = {
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_1] = { 1, 1 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_6_7] = { 6, 7 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_4_5] = { 4, 5 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_3_4] = { 3, 4 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_5_7] = { 5, 7 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_2_3] = { 2, 3 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_3_5] = { 3, 5 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_4_7] = { 4, 7 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_2_4] = { 2, 4 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_3_7] = { 3, 7 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_2_5] = { 2, 5 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_1_3] = { 1, 3 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_2_7] = { 2, 7 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_1_5] = { 1, 5 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_1_7] = { 1, 7 },
|
|
[TX3912_VIDEO_DITHER_DUTYCYCLE_0] = { 0, 1 }
|
|
}, *dlp;
|
|
|
|
static const int dither_level8[8] = {
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_0,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_2_7,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_2_5,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_2_4,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_3_5,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_5_7,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_4_5,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_1,
|
|
};
|
|
|
|
static const int dither_level4[4] = {
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_0,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_1_3,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_5_7,
|
|
TX3912_VIDEO_DITHER_DUTYCYCLE_1,
|
|
};
|
|
|
|
static int
|
|
__get_color8(luti)
|
|
int luti;
|
|
{
|
|
KASSERT(luti >=0 && luti < 8);
|
|
dlp = &dither_list[dither_level8[luti]];
|
|
|
|
return ((0xff * dlp->mul) / dlp->div);
|
|
}
|
|
|
|
static int
|
|
__get_color4(luti)
|
|
int luti;
|
|
{
|
|
KASSERT(luti >=0 && luti < 4);
|
|
dlp = &dither_list[dither_level4[luti]];
|
|
|
|
return ((0xff * dlp->mul) / dlp->div);
|
|
}
|
|
|
|
void
|
|
tx3912video_clut_get(sc, rgb, beg, cnt)
|
|
struct tx3912video_softc *sc;
|
|
u_int32_t *rgb;
|
|
int beg, cnt;
|
|
{
|
|
int i;
|
|
|
|
KASSERT(rgb);
|
|
KASSERT(LEGAL_CLUT_INDEX(beg));
|
|
KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1));
|
|
|
|
for (i = beg; i < beg + cnt; i++) {
|
|
*rgb++ = RGB24(__get_color8((i >> 5) & 0x7),
|
|
__get_color8((i >> 2) & 0x7),
|
|
__get_color4(i & 0x3));
|
|
}
|
|
}
|
|
|
|
void
|
|
tx3912video_clut_install(ctx, ri)
|
|
void *ctx;
|
|
struct rasops_info *ri;
|
|
{
|
|
struct tx3912video_softc *sc = ctx;
|
|
const int system_cmap[0x10] = {
|
|
TX3912VIDEO_BLACK,
|
|
TX3912VIDEO_RED,
|
|
TX3912VIDEO_GREEN,
|
|
TX3912VIDEO_YELLOW,
|
|
TX3912VIDEO_BLUE,
|
|
TX3912VIDEO_MAGENTA,
|
|
TX3912VIDEO_CYAN,
|
|
TX3912VIDEO_WHITE,
|
|
TX3912VIDEO_DARK_BLACK,
|
|
TX3912VIDEO_DARK_RED,
|
|
TX3912VIDEO_DARK_GREEN,
|
|
TX3912VIDEO_DARK_YELLOW,
|
|
TX3912VIDEO_DARK_BLUE,
|
|
TX3912VIDEO_DARK_MAGENTA,
|
|
TX3912VIDEO_DARK_CYAN,
|
|
TX3912VIDEO_DARK_WHITE,
|
|
};
|
|
|
|
KASSERT(ri);
|
|
|
|
if (sc->sc_chip->vc_fbdepth == 8) {
|
|
/* XXX 2bit gray scale LUT not supported */
|
|
memcpy(ri->ri_devcmap, system_cmap, sizeof system_cmap);
|
|
}
|
|
}
|
|
|
|
void
|
|
tx3912video_clut_init(sc)
|
|
struct tx3912video_softc *sc;
|
|
{
|
|
tx_chipset_tag_t tc = sc->sc_chip->vc_tc;
|
|
|
|
if (sc->sc_chip->vc_fbdepth != 8) {
|
|
return; /* XXX 2bit gray scale LUT not supported */
|
|
}
|
|
|
|
/*
|
|
* time-based dithering pattern (TOSHIBA recommended pattern)
|
|
*/
|
|
/* 2/3, 1/3 */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL8_REG,
|
|
TX3912_VIDEOCTRL8_PAT2_3_DEFAULT);
|
|
/* 3/4, 2/4 */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL9_REG,
|
|
(TX3912_VIDEOCTRL9_PAT3_4_DEFAULT << 16) |
|
|
TX3912_VIDEOCTRL9_PAT2_4_DEFAULT);
|
|
/* 4/5, 1/5 */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL10_REG,
|
|
TX3912_VIDEOCTRL10_PAT4_5_DEFAULT);
|
|
/* 3/5, 2/5 */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL11_REG,
|
|
TX3912_VIDEOCTRL11_PAT3_5_DEFAULT);
|
|
/* 6/7, 1/7 */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL12_REG,
|
|
TX3912_VIDEOCTRL12_PAT6_7_DEFAULT);
|
|
/* 5/7, 2/7 */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL13_REG,
|
|
TX3912_VIDEOCTRL13_PAT5_7_DEFAULT);
|
|
/* 4/7, 3/7 */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL14_REG,
|
|
TX3912_VIDEOCTRL14_PAT4_7_DEFAULT);
|
|
|
|
/*
|
|
* dither-pattern look-up table. (selected by uch)
|
|
*/
|
|
/* red */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL5_REG,
|
|
(dither_level8[7] << 28) |
|
|
(dither_level8[6] << 24) |
|
|
(dither_level8[5] << 20) |
|
|
(dither_level8[4] << 16) |
|
|
(dither_level8[3] << 12) |
|
|
(dither_level8[2] << 8) |
|
|
(dither_level8[1] << 4) |
|
|
(dither_level8[0] << 0));
|
|
/* green */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL6_REG,
|
|
(dither_level8[7] << 28) |
|
|
(dither_level8[6] << 24) |
|
|
(dither_level8[5] << 20) |
|
|
(dither_level8[4] << 16) |
|
|
(dither_level8[3] << 12) |
|
|
(dither_level8[2] << 8) |
|
|
(dither_level8[1] << 4) |
|
|
(dither_level8[0] << 0));
|
|
/* blue (2bit gray scale also use this look-up table) */
|
|
tx_conf_write(tc, TX3912_VIDEOCTRL7_REG,
|
|
(dither_level4[3] << 12) |
|
|
(dither_level4[2] << 8) |
|
|
(dither_level4[1] << 4) |
|
|
(dither_level4[0] << 0));
|
|
|
|
tx3912video_reset(sc->sc_chip);
|
|
}
|
|
|
|
/*
|
|
* Debug routines.
|
|
*/
|
|
void
|
|
tx3912video_calibration_pattern()
|
|
{
|
|
struct tx3912video_chip *vc = &tx3912video_chip;
|
|
int x, y;
|
|
|
|
x = vc->vc_fbwidth - 40;
|
|
y = vc->vc_fbheight - 40;
|
|
tx3912video_line(40, 40, x , 40);
|
|
tx3912video_line(x , 40, x , y );
|
|
tx3912video_line(x , y , 40, y );
|
|
tx3912video_line(40, y , 40, 40);
|
|
tx3912video_line(40, 40, x , y );
|
|
tx3912video_line(x, 40, 40, y );
|
|
}
|
|
|
|
#define BPP2 ({ \
|
|
u_int8_t bitmap; \
|
|
bitmap = *(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr); \
|
|
*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = \
|
|
(bitmap & ~(0x3 << ((3 - (x % 4)) * 2))); \
|
|
})
|
|
|
|
#define BPP4 ({ \
|
|
u_int8_t bitmap; \
|
|
bitmap = *(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr); \
|
|
*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = \
|
|
(bitmap & ~(0xf << ((1 - (x % 2)) * 4))); \
|
|
})
|
|
|
|
#define BPP8 ({ \
|
|
*(volatile u_int8_t*)MIPS_PHYS_TO_KSEG1(addr) = 0xff; \
|
|
})
|
|
|
|
#define BRESENHAM(a, b, c, d, func) ({ \
|
|
u_int32_t fbaddr = vc->vc_fbaddr; \
|
|
u_int32_t fbwidth = vc->vc_fbwidth; \
|
|
u_int32_t fbdepth = vc->vc_fbdepth; \
|
|
len = a, step = b -1; \
|
|
if (step == 0) \
|
|
return; \
|
|
kstep = len == 0 ? 0 : 1; \
|
|
for (i = k = 0, j = step / 2; i <= step; i++) { \
|
|
x = xbase c; \
|
|
y = ybase d; \
|
|
addr = fbaddr + (((y * fbwidth + x) * fbdepth) >> 3); \
|
|
func; \
|
|
j -= len; \
|
|
while (j < 0) { \
|
|
j += step; \
|
|
k += kstep; \
|
|
} \
|
|
} \
|
|
})
|
|
|
|
#define DRAWLINE(func) ({ \
|
|
if (x < 0) { \
|
|
if (y < 0) { \
|
|
if (_y < _x) { \
|
|
BRESENHAM(_y, _x, -i, -k, func); \
|
|
} else { \
|
|
BRESENHAM(_x, _y, -k, -i, func); \
|
|
} \
|
|
} else { \
|
|
if (_y < _x) { \
|
|
BRESENHAM(_y, _x, -i, +k, func); \
|
|
} else { \
|
|
BRESENHAM(_x, _y, -k, +i, func); \
|
|
} \
|
|
} \
|
|
} else { \
|
|
if (y < 0) { \
|
|
if (_y < _x) { \
|
|
BRESENHAM(_y, _x, +i, -k, func); \
|
|
} else { \
|
|
BRESENHAM(_x, _y, +k, -i, func); \
|
|
} \
|
|
} else { \
|
|
if (_y < _x) { \
|
|
BRESENHAM(_y, _x, +i, +k, func); \
|
|
} else { \
|
|
BRESENHAM(_x, _y, +k, +i, func); \
|
|
} \
|
|
} \
|
|
} \
|
|
})
|
|
|
|
#define LINEFUNC(b) \
|
|
static void linebpp##b __P((int, int, int, int)); \
|
|
static void \
|
|
linebpp##b##(x0, y0, x1, y1) \
|
|
int x0, y0, x1, y1; \
|
|
{ \
|
|
struct tx3912video_chip *vc = &tx3912video_chip; \
|
|
u_int32_t addr; \
|
|
int i, j, k, len, step, kstep; \
|
|
int x, _x, y, _y; \
|
|
int xbase, ybase; \
|
|
x = x1 - x0; \
|
|
y = y1 - y0; \
|
|
_x = abs(x); \
|
|
_y = abs(y); \
|
|
xbase = x0; \
|
|
ybase = y0; \
|
|
DRAWLINE(BPP##b##); \
|
|
}
|
|
|
|
#define DOTFUNC(b) \
|
|
static void dotbpp##b __P((int, int)); \
|
|
static void \
|
|
dotbpp##b##(x, y) \
|
|
int x, y; \
|
|
{ \
|
|
struct tx3912video_chip *vc = &tx3912video_chip; \
|
|
u_int32_t addr; \
|
|
addr = vc->vc_fbaddr + (((y * vc->vc_fbwidth + x) * \
|
|
vc->vc_fbdepth) >> 3); \
|
|
BPP##b; \
|
|
}
|
|
|
|
static void linebpp_unimpl __P((int, int, int, int));
|
|
static void dotbpp_unimpl __P((int, int));
|
|
static
|
|
void linebpp_unimpl(x0, y0, x1, y1)
|
|
int x0, y0, x1, y1;
|
|
{
|
|
return;
|
|
}
|
|
static
|
|
void dotbpp_unimpl(x, y)
|
|
int x, y;
|
|
{
|
|
return;
|
|
}
|
|
|
|
LINEFUNC(2)
|
|
LINEFUNC(4)
|
|
LINEFUNC(8)
|
|
DOTFUNC(2)
|
|
DOTFUNC(4)
|
|
DOTFUNC(8)
|
|
|
|
void
|
|
__tx3912video_attach_drawfunc(vc)
|
|
struct tx3912video_chip *vc;
|
|
{
|
|
switch (vc->vc_fbdepth) {
|
|
default:
|
|
vc->vc_drawline = linebpp_unimpl;
|
|
vc->vc_drawdot = dotbpp_unimpl;
|
|
break;
|
|
case 8:
|
|
vc->vc_drawline = linebpp8;
|
|
vc->vc_drawdot = dotbpp8;
|
|
break;
|
|
case 4:
|
|
vc->vc_drawline = linebpp4;
|
|
vc->vc_drawdot = dotbpp4;
|
|
break;
|
|
case 2:
|
|
vc->vc_drawline = linebpp2;
|
|
vc->vc_drawdot = dotbpp2;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void
|
|
tx3912video_line(x0, y0, x1, y1)
|
|
int x0, y0, x1, y1;
|
|
{
|
|
struct tx3912video_chip *vc = &tx3912video_chip;
|
|
if (vc->vc_drawline)
|
|
vc->vc_drawline(x0, y0, x1, y1);
|
|
}
|
|
|
|
void
|
|
tx3912video_dot(x, y)
|
|
int x, y;
|
|
{
|
|
struct tx3912video_chip *vc = &tx3912video_chip;
|
|
if (vc->vc_drawdot)
|
|
vc->vc_drawdot(x, y);
|
|
}
|