281 lines
7.6 KiB
ArmAsm
281 lines
7.6 KiB
ArmAsm
/* $NetBSD: bzero.S,v 1.2 1999/12/30 15:31:39 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993, 1999
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Header: bzero.s,v 1.1 92/06/25 12:52:46 torek Exp
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*/
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#include <machine/asm.h>
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#ifndef _LOCORE
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#define _LOCORE
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#endif
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#include <machine/ctlreg.h>
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#include <machine/frame.h>
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#include <machine/psl.h>
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#if defined(LIBC_SCCS) && !defined(lint)
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#if 0
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.asciz "@(#)bzero.s 8.1 (Berkeley) 6/4/93"
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#else
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RCSID("$NetBSD: bzero.S,v 1.2 1999/12/30 15:31:39 eeh Exp $")
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#endif
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#endif /* LIBC_SCCS and not lint */
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#ifdef MEMSET
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/*
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* memset(addr, c, len)
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*
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* Duplicate the pattern so it fills 64-bits, then swap around the
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* arguments and call bzero.
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*/
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ENTRY(memset)
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and %o1, 0x0ff, %o3
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mov %o2, %o1
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sllx %o3, 8, %o2
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or %o2, %o3, %o2
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mov %o0, %o4 ! Save original pointer
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sllx %o2, 16, %o3
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or %o2, %o3, %o2
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sllx %o2, 32, %o3
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or %o2, %o3, %o2
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#else
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/*
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* bzero(addr, len)
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*
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* We want to use VIS instructions if we're clearing out more than
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* 256 bytes, but to do that we need to properly save and restore the
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* FP registers. Unfortunately the code to do that in the kernel needs
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* to keep track of the current owner of the FPU, hence the different
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* code.
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*
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*/
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ENTRY(bzero)
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! %o0 = addr, %o1 = len
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clr %o2 ! Initialize our pattern
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#endif
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Lbzero_internal:
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brz,pn %o1, Lbzero_done ! No bytes to copy??
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! cmp %o1, 8 ! Less than 8 bytes to go?
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! ble,a,pn %icc, Lbzero_small ! Do it byte at a time.
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! deccc 8, %o1 ! pre-decrement
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btst 7, %o0 ! 64-bit aligned? Optimization
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bz,pt %xcc, 2f
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btst 3, %o0 ! 32-bit aligned?
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bz,pt %xcc, 1f
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btst 1, %o0 ! 16-bit aligned?
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bz,pt %xcc, 0f
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btst 3, %o0
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!! unaligned -- store 1 byte
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stb %o2, [%o0]
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dec 1, %o1 ! Record storing 1 byte
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inc %o0
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cmp %o1, 2
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bl,a,pn %icc, 7f ! 1 or 0 left
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dec 8, %o1 ! Fixup count -8
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0:
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btst 3, %o0
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bz,pt %xcc, 1f
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btst 7, %o0 ! 64-bit aligned?
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!! 16-bit aligned -- store half word
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sth %o2, [%o0]
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dec 2, %o1 ! Prepare to store 2 bytes
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inc 2, %o0
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cmp %o1, 4
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bl,a,pn %icc, 5f ! Less than 4 left
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dec 8, %o1 ! Fixup count -8
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1:
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btst 7, %o0 ! 64-bit aligned?
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bz,pt %xcc, 2f
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nop
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!! 32-bit aligned -- store word
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stw %o2, [%o0]
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dec 4, %o1
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inc 4, %o0
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cmp %o1, 8
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bl,a,pn %icc, Lbzero_cleanup ! Less than 8 left
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dec 8, %o1 ! Fixup count -8
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2:
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!! Now we're 64-bit aligned
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cmp %o1, 256 ! Use block clear if len > 256
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bge,pt %xcc, Lbzero_block ! use block store insns
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deccc 8, %o1
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Lbzero_longs:
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bl,pn %xcc, Lbzero_cleanup ! Less than 8 bytes left
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nop
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3:
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stx %o2, [%o0] ! Do 1 longword at a time
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deccc 8, %o1
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bge,pt %xcc, 3b
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inc 8, %o0
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/*
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* Len is in [-8..-1] where -8 => done, -7 => 1 byte to zero,
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* -6 => two bytes, etc. Mop up this remainder, if any.
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*/
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Lbzero_cleanup:
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btst 4, %o1
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bz,pt %xcc, 6f ! if (len & 4) {
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btst 2, %o1
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stw %o2, [%o0] ! *(int *)addr = 0;
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inc 4, %o0 ! addr += 4;
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5:
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btst 2, %o1
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6:
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bz,pt %xcc, 8f ! if (len & 2) {
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btst 1, %o1
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sth %o2, [%o0] ! *(short *)addr = 0;
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inc 2, %o0 ! addr += 2;
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7:
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btst 1, %o1
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8:
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bnz,a %icc, Lbzero_done ! if (len & 1)
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stb %o2, [%o0] ! *addr = 0;
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Lbzero_done:
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retl
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mov %o4, %o0 ! Restore ponter for memset (ugh)
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/*
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* Len is in [-8..-1] where -8 => done, -7 => 1 byte to zero,
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* -6 => two bytes, etc. but we're potentially unaligned.
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* Do byte stores since it's easiest.
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*/
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Lbzero_small:
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inccc 8, %o1
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bz,pn %icc, Lbzero_done
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1:
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deccc %o1
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stb %o2, [%o0]
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bge,pt %icc, 1b
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inc %o0
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ba,a,pt %icc, Lbzero_done
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nop ! XXX spitfire bug?
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Lbzero_block:
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/*
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* Userland:
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*
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* We allocate enough space on the stack to save our registers and save
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* our floating point state. We really don't need to do this if the
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* registers were not in use before, but we can't really tell if they
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* were in use or not.
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*
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* See locore.s for the kernel version.
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*
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*/
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save %sp, -(CC64FSZ+32*8+BLOCK_SIZE), %sp ! Allocate an fpstate
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add %sp, (CC64FSZ+BLOCK_SIZE-1), %l0 ! Calculate pointer to fpstate
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andn %l0, BLOCK_ALIGN, %l0 ! And make it block aligned
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btst 1, %sp
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add %l0, BIAS, %l1 ! Fixup 64-bit stack pointers
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movnz %xcc, %l1, %l0
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! wr %g0, FPRS_FEF, %fprs ! Enable FPU
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stda %f0, [%l0] ASI_BLK_P
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add %l0, BLOCK_SIZE, %l1
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stda %f16, [%l1] ASI_BLK_COMMIT_P ! We only need two banks
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!! We are now 8-byte aligned. We need to become 64-byte aligned.
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btst 63, %i0
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bz,pt %xcc, 2f
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nop
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1:
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stx %i2, [%i0]
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inc 8, %i0
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btst 63, %i0
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bnz,pt %xcc, 1b
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dec 8, %i1
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2:
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brz,pt %i2, 4f ! Do we have a pattern to load?
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fzero %f0 ! Set up FPU
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btst 1, %fp
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bnz,pt %icc, 3f ! 64-bit stack?
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nop
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stw %i2, [%fp + 0x28] ! Flush this puppy to RAM
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membar #StoreLoad
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ld [%fp + 0x28], %f0
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ba,pt %icc, 4f
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fmovsa %icc, %f0, %f1
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3:
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stx %i2, [%fp + BIAS + 0x50] ! Flush this puppy to RAM
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membar #StoreLoad
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ldd [%fp + BIAS + 0x50], %f0
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4:
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fmovda %icc, %f0, %f2 ! Duplicate the pattern
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fmovda %icc, %f0, %f4
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fmovda %icc, %f0, %f6
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fmovda %icc, %f0, %f8
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fmovda %icc, %f0, %f10
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fmovda %icc, %f0, %f12
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fmovda %icc, %f0, %f14
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fmovda %icc, %f0, %f16 ! And second bank
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fmovda %icc, %f0, %f18
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fmovda %icc, %f0, %f20
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fmovda %icc, %f0, %f22
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fmovda %icc, %f0, %f24
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fmovda %icc, %f0, %f26
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fmovda %icc, %f0, %f28
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fmovda %icc, %f0, %f30
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!! Remember: we were 8 bytes too far
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dec 56, %i1 ! Go one iteration too far
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5:
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stda %f0, [%i0] ASI_BLK_COMMIT_P ! Store 64 bytes
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deccc 64, %i1
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ble,pn %xcc, 6f
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inc 64, %i0
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stda %f0, [%i0] ASI_BLK_COMMIT_P ! Store 64 bytes
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deccc 64, %i1
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bg,pn %xcc, 5b
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inc 64, %i0
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6:
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/*
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* Now we're done we need to load the FPU state from where
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* we put it.
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*/
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ldda [%l0] ASI_BLK_P, %f0
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add %l0, BLOCK_SIZE, %l1
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ldda [%l1] ASI_BLK_P, %f16
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addcc %i1, 56, %i1 ! Restore the count
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ba,pt %xcc, Lbzero_longs ! Finish up the remainder
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restore
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