wdk b697919ea7 Add bus_dmamap_sync for pre-read and pre-write case. This was previously ...

left out as it was a no-op on the R3000 processor.  However, recent changes
to the Mips cache ops highlighted we should DTRT in case the MI/MD layer
choses to invalidate the cache ahead of the DMA instead of after it.

2001-12-15 11:11:49 +00:00

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asc.c

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clockreg.h

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i82072.c

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if_le.c

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mkclock.c

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obio.c

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rambo.c

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rambo.h

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zs_kgdb.c

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zs.c

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