396 lines
10 KiB
C
396 lines
10 KiB
C
/* $NetBSD: z8530sc.c,v 1.1 1996/05/18 18:54:28 briggs Exp $ */
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/*
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)zs.c 8.1 (Berkeley) 7/19/93
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*/
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/*
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* Zilog Z8530 Dual UART driver (common part)
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*
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* This file contains the machine-independent parts of the
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* driver common to tty and keyboard/mouse sub-drivers.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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/* #include <dev/ic/z8530reg.h> */
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#include "z8530reg.h"
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#include <machine/z8530var.h>
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int
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zs_break(cs, set)
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struct zs_chanstate *cs;
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int set;
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{
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int s;
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s = splzs();
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if (set) {
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cs->cs_preg[5] |= ZSWR5_BREAK;
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cs->cs_creg[5] |= ZSWR5_BREAK;
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} else {
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cs->cs_preg[5] &= ~ZSWR5_BREAK;
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cs->cs_creg[5] &= ~ZSWR5_BREAK;
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}
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zs_write_reg(cs, 5, cs->cs_creg[5]);
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splx(s);
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return 0;
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}
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/*
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* Compute the current baud rate given a ZSCC channel.
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*/
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int
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zs_getspeed(cs)
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struct zs_chanstate *cs;
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{
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int tconst;
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tconst = zs_read_reg(cs, 12);
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tconst |= zs_read_reg(cs, 13) << 8;
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return (TCONST_TO_BPS(cs->cs_pclk_div16, tconst));
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}
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/*
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* drain on-chip fifo
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*/
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void
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zs_iflush(cs)
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struct zs_chanstate *cs;
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{
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u_char c, rr0, rr1;
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for (;;) {
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/* Is there input available? */
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rr0 = zs_read_csr(cs);
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if ((rr0 & ZSRR0_RX_READY) == 0)
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break;
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/*
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* First read the status, because reading the data
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* destroys the status of this char.
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*/
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rr1 = zs_read_reg(cs, 1);
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c = zs_read_data(cs);
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if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) {
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/* Clear the receive error. */
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zs_write_csr(cs, ZSWR0_RESET_ERRORS);
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}
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}
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}
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/*
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* Figure out if a chip is an NMOS 8530, a CMOS 8530,
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* or an 85230. We use a form of the test in the Zilog SCC
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* users manual.
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*/
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int
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zs_checkchip(cs)
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struct zs_chanstate *cs;
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{
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char r1, r2, r3;
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int chip;
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/* we assume we can write to the chip */
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r1=cs->cs_creg[15]; /* see if bit 0 sticks */
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zs_write_reg(cs, 15, (r1 | ZSWR15_ENABLE_ENHANCED));
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if ((zs_read_reg(cs, 15) & ZSWR15_ENABLE_ENHANCED) != 0) {
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/* we have either an 8580 or 85230. NB Zilog says we should only
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* have an 85230 at this point, but the 8580 seems to pass this
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* test too. To test, we try to write to WR7', and see if we
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* loose sight of RR14. */
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r2=cs->cs_creg[14];
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r3=(r2 != 0x47) ? 0x47 : 0x40;
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/* unique bit pattern to turn on reading of WR7' at RR14 */
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zs_write_reg(cs, 7, ~r2);
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if (zs_read_reg(cs, ZSRR_ENHANCED) != r2) {
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chip = ZS_CHIP_ESCC;
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zs_write_reg(cs, 7, cs->cs_creg[ZS_ENHANCED_REG]);
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} else {
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chip = ZS_CHIP_8580;
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zs_write_reg(cs, 7, cs->cs_creg[7]);
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}
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zs_write_reg(cs, 15, r1);
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} else { /* now we have to tell an NMOS from a CMOS; does WR15 D2 work? */
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zs_write_reg(cs, 15, (r1 | ZSWR15_SDLC_FIFO));
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r2=cs->cs_creg[2];
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zs_write_reg(cs, 2, (r2 | 0x80));
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chip = (zs_read_reg(cs, 6) & 0x80) ? ZS_CHIP_NMOS : ZS_CHIP_CMOS;
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zs_write_reg(cs, 2, r2);
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}
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zs_write_reg(cs, 15, r1);
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return chip;
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}
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/*
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* Write the given register set to the given zs channel in the proper order.
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* The channel must not be transmitting at the time. The receiver will
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* be disabled for the time it takes to write all the registers.
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* Call this with interrupts disabled.
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*/
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void
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zs_loadchannelregs(cs)
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struct zs_chanstate *cs;
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{
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u_char *reg;
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/* Copy "pending" regs to "current" */
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bcopy((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16);
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reg = cs->cs_creg; /* current regs */
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zs_write_csr(cs, ZSM_RESET_ERR); /* XXX: reset error condition */
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#if 1
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/*
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* XXX: Is this really a good idea?
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* XXX: Should go elsewhere! -gwr
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*/
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zs_iflush(cs); /* XXX */
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#endif
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/* disable interrupts */
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zs_write_reg(cs, 1, reg[1] &
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~(ZSWR1_RIE_SPECIAL_ONLY | ZSWR1_TIE | ZSWR1_SIE));
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/* baud clock divisor, stop bits, parity */
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zs_write_reg(cs, 4, reg[4]);
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/* misc. TX/RX control bits */
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zs_write_reg(cs, 10, reg[10]);
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/* char size, enable (RX/TX) */
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zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
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zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
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/* synchronous mode stuff */
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zs_write_reg(cs, 6, reg[6]);
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zs_write_reg(cs, 7, reg[7]);
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#if 0
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/*
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* Registers 2 and 9 are special because they are
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* actually common to both channels, but must be
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* programmed through channel A. The "zsc" attach
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* function takes care of setting these registers
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* and they should not be touched thereafter.
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*/
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/* interrupt vector */
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zs_write_reg(cs, 2, reg[2]);
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/* master interrupt control */
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zs_write_reg(cs, 9, reg[9]);
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#endif
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/* Shut down the BRG */
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zs_write_reg(cs, 14, reg[14] & ~ZSWR14_BAUD_ENA);
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if ((cs->cs_cclk_flag & ZSC_EXTERN) ||
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(cs->cs_pclk_flag & ZSC_EXTERN))
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zsmd_setclock(cs);
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/* the md layer wants to do something; let it. */
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/* clock mode control */
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zs_write_reg(cs, 11, reg[11]);
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/* baud rate (lo/hi) */
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zs_write_reg(cs, 12, reg[12]);
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zs_write_reg(cs, 13, reg[13]);
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/* Misc. control bits */
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zs_write_reg(cs, 14, reg[14]);
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/* which lines cause status interrupts */
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zs_write_reg(cs, 15, reg[15]);
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/* Zilog docs recommend resetting external status twice at this
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* point. Mainly as the status bits are latched, and the first
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* interrupt clear might unlatch them to new values, generating
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* a second interrupt request.
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*/
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zs_write_csr(cs, ZSM_RESET_STINT);
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zs_write_csr(cs, ZSM_RESET_STINT);
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/* char size, enable (RX/TX)*/
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zs_write_reg(cs, 3, reg[3]);
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zs_write_reg(cs, 5, reg[5]);
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/* interrupt enables: TX, TX, STATUS */
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zs_write_reg(cs, 1, reg[1]);
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cs->cs_cclk_flag = cs->cs_pclk_flag;
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cs->cs_csource = cs->cs_psource;
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}
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/*
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* ZS hardware interrupt. Scan all ZS channels. NB: we know here that
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* channels are kept in (A,B) pairs.
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*
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* Do just a little, then get out; set a software interrupt if more
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* work is needed.
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*
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* We deliberately ignore the vectoring Zilog gives us, and match up
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* only the number of `reset interrupt under service' operations, not
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* the order.
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*/
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int
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zsc_intr_hard(arg)
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void *arg;
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{
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register struct zsc_softc *zsc = arg;
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register struct zs_chanstate *cs_a;
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register struct zs_chanstate *cs_b;
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register int rval;
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register u_char rr3;
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cs_a = &zsc->zsc_cs[0];
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cs_b = &zsc->zsc_cs[1];
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rval = 0;
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/* Note: only channel A has an RR3 */
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rr3 = zs_read_reg(cs_a, 3);
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/* Handle receive interrupts first. */
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if (rr3 & ZSRR3_IP_A_RX)
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(*cs_a->cs_ops->zsop_rxint)(cs_a);
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if (rr3 & ZSRR3_IP_B_RX)
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(*cs_b->cs_ops->zsop_rxint)(cs_b);
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/* Handle status interrupts (i.e. flow control). */
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if (rr3 & ZSRR3_IP_A_STAT)
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(*cs_a->cs_ops->zsop_stint)(cs_a);
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if (rr3 & ZSRR3_IP_B_STAT)
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(*cs_b->cs_ops->zsop_stint)(cs_b);
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/* Handle transmit done interrupts. */
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if (rr3 & ZSRR3_IP_A_TX)
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(*cs_a->cs_ops->zsop_txint)(cs_a);
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if (rr3 & ZSRR3_IP_B_TX)
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(*cs_b->cs_ops->zsop_txint)(cs_b);
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/* Clear interrupt. */
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if (rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT)) {
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zs_write_csr(cs_a, ZSWR0_CLR_INTR);
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rval |= 1;
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}
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if (rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) {
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zs_write_csr(cs_b, ZSWR0_CLR_INTR);
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rval |= 2;
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}
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if ((cs_a->cs_softreq) || (cs_b->cs_softreq)) {
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/* This is a machine-dependent function (or macro). */
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zsc_req_softint(zsc);
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}
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return (rval);
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}
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/*
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* ZS software interrupt. Scan all channels for deferred interrupts.
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*/
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int
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zsc_intr_soft(arg)
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void *arg;
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{
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register struct zsc_softc *zsc = arg;
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register struct zs_chanstate *cs;
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register int rval, unit;
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rval = 0;
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for (unit = 0; unit < 2; unit++) {
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cs = &zsc->zsc_cs[unit];
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/*
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* The softint flag can be safely cleared once
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* we have decided to call the softint routine.
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* (No need to do splzs() first.)
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*/
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if (cs->cs_softreq) {
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cs->cs_softreq = 0;
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(*cs->cs_ops->zsop_softint)(cs);
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rval = 1;
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}
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}
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return (rval);
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}
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static void zsnull_intr __P((struct zs_chanstate *));
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static void zsnull_softint __P((struct zs_chanstate *));
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static void
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zsnull_intr(cs)
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struct zs_chanstate *cs;
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{
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zs_write_reg(cs, 1, 0);
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zs_write_reg(cs, 15, 0);
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}
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static void
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zsnull_softint(cs)
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struct zs_chanstate *cs;
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{
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}
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struct zsops zsops_null = {
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zsnull_intr, /* receive char available */
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zsnull_intr, /* external/status */
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zsnull_intr, /* xmit buffer empty */
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zsnull_softint, /* process software interrupt */
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};
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