267 lines
9.6 KiB
C
267 lines
9.6 KiB
C
/* $NetBSD: cgsixreg.h,v 1.6 2005/05/16 14:29:11 macallan Exp $ */
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/*
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* Copyright (c) 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cgsixreg.h 8.4 (Berkeley) 1/21/94
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*/
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/*
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* CG6 display registers. (Note, I got tired of writing `cgsix' about
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* halfway through and changed everything to cg6, but I probably missed
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* some. Unfortunately, the way config works, we need to spell out `six'
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* in some places anyway.)
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*
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* The cg6 is a complicated beastie. We have been unable to extract any
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* documentation and most of the following are guesses based on a limited
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* amount of reverse engineering.
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*
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* A cg6 is composed of numerous groups of control registers, all with TLAs:
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* FBC - frame buffer control?
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* FHC - fbc hardware configuration / control? register (32 bits)
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* DHC - ???
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* TEC - transform engine control?
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* THC - TEC Hardware Configuration
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* ROM - a 64Kbyte ROM with who knows what in it.
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* colormap - see below
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* frame buffer memory (video RAM)
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* possible other stuff
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*
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* Like the cg3, the cg6 uses a Brooktree Video DAC (see btreg.h).
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*
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* Various revisions of the cgsix have various hardware bugs. So far,
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* we have only seen rev 1 & 2.
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*/
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/* Control register banks offsets */
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#define CGSIX_ROM_OFFSET 0x000000
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#define CGSIX_BT_OFFSET 0x200000
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#define CGSIX_DHC_OFFSET 0x240000
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#define CGSIX_ALT_OFFSET 0x280000
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#define CGSIX_FHC_OFFSET 0x300000
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#define CGSIX_THC_OFFSET 0x301000
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#define CGSIX_FBC_OFFSET 0x700000
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#define CGSIX_TEC_OFFSET 0x701000
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#define CGSIX_RAM_OFFSET 0x800000
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/* bits in FHC register */
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#define FHC_FBID_MASK 0xff000000 /* bits 24..31 are frame buffer ID */
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#define FHC_FBID_SHIFT 24
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#define FHC_REV_MASK 0x00f00000 /* bits 20..23 are revision */
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#define FHC_REV_SHIFT 20
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#define FHC_FROP_DISABLE 0x00080000 /* disable fast/font? rasterops */
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#define FHC_ROW_DISABLE 0x00040000 /* ??? */
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#define FHC_SRC_DISABLE 0x00020000 /* ??? */
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#define FHC_DST_DISABLE 0x00010000 /* disable destination cache */
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#define FHC_RESET 0x00008000 /* ??? */
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#define FHC_XXX0 0x00004000 /* ??? */
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#define FHC_LEBO 0x00002000 /* set little endian byte order? */
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#define FHC_RES_MASK 0x00001800 /* bits 11&12 are resolution */
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#define FHC_RES_1024 0x00000000 /* res = 1024x768 */
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#define FHC_RES_1152 0x00000800 /* res = 1152x900 */
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#define FHC_RES_1280 0x00001000 /* res = 1280x1024 */
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#define FHC_RES_1600 0x00001800 /* res = 1600x1200 */
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#define FHC_CPU_MASK 0x00000600 /* bits 9&10 are cpu type */
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#define FHC_CPU_SPARC 0x00000000 /* cpu = sparc */
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#define FHC_CPU_68020 0x00000200 /* cpu = 68020 */
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#define FHC_CPU_386 0x00000400 /* cpu = 80386 */
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#define FHC_CPU_XXX 0x00000600 /* ??? */
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#define FHC_TEST 0x00000100 /* ??? test window ??? */
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#define FHC_TESTX_MASK 0x000000f0 /* bits 4..7 are test window X */
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#define FHC_TESTX_SHIFT 4
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#define FHC_TESTY_MASK 0x0000000f /* bits 0..3 are test window Y */
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#define FHC_TESTY_SHIFT 0
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/*
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* The layout of the THC.
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*/
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struct cg6_thc {
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u_int32_t thc_xxx0[512]; /* ??? */
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u_int32_t thc_hsync1; /* horizontal sync timing */
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u_int32_t thc_hsync2; /* more hsync timing */
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u_int32_t thc_hsync3; /* yet more hsync timing */
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u_int32_t thc_vsync1; /* vertical sync timing */
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u_int32_t thc_vsync2; /* only two of these */
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u_int32_t thc_refresh; /* refresh counter */
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u_int32_t thc_misc; /* miscellaneous control & status */
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u_int32_t thc_xxx1[56]; /* ??? */
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u_int32_t thc_cursxy; /* cursor x,y position (16 bits each) */
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u_int32_t thc_cursmask[32];/* cursor mask bits */
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u_int32_t thc_cursbits[32];/* what to show where mask enabled */
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};
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/* bits in thc_misc */
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#define THC_MISC_XXX0 0xfff00000 /* unused */
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#define THC_MISC_REVMASK 0x000f0000 /* cg6 revision? */
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#define THC_MISC_REVSHIFT 16
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#define THC_MISC_XXX1 0x0000e000 /* unused */
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#define THC_MISC_RESET 0x00001000 /* ??? */
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#define THC_MISC_XXX2 0x00000800 /* unused */
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#define THC_MISC_VIDEN 0x00000400 /* video enable */
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#define THC_MISC_SYNC 0x00000200 /* not sure what ... */
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#define THC_MISC_VSYNC 0x00000100 /* ... these really are */
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#define THC_MISC_SYNCEN 0x00000080 /* sync enable */
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#define THC_MISC_CURSRES 0x00000040 /* cursor resolution */
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#define THC_MISC_INTEN 0x00000020 /* v.retrace intr enable */
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#define THC_MISC_INTR 0x00000010 /* intr pending / ack bit */
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#define THC_MISC_XXX 0x0000000f /* ??? */
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/* cursor x / y position value for `off' */
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#define THC_CURSOFF (65536-32) /* i.e., USHRT_MAX+1-32 */
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/*
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* Partial description of TEC (needed to get around FHC rev 1 bugs).
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*/
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struct cg6_tec_xxx {
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u_int32_t tec_mv; /* matrix stuff */
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u_int32_t tec_clip; /* clipping stuff */
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u_int32_t tec_vdc; /* ??? */
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};
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/*
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* Partial description of FBC
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*
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* Most of this we don't care about; here are only the portions
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* we need, most notably the blitter. Comments are merely my
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* best guesses as to register functions, based largely on the
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* X11R6.4 sunGX code. Some of these are here only so we can
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* stuff canned values in them (eg, offx).
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*/
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struct cg6_fbc {
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u_int32_t fbc_pad1[1];
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u_int32_t fbc_mode; /* mode setting */
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u_int32_t fbc_clip; /* function unknown */
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u_int32_t fbc_pad2[1];
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u_int32_t fbc_s; /* global status */
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u_int32_t fbc_draw; /* drawing pipeline status */
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u_int32_t fbc_blit; /* blitter status */
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u_int32_t fbc_font; /* pixel transfer register */
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u_int32_t fbc_pad3[24];
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u_int32_t fbc_x0; /* blitter, src llx */
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u_int32_t fbc_y0; /* blitter, src lly */
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u_int32_t fbc_pad4[2];
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u_int32_t fbc_x1; /* blitter, src urx */
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u_int32_t fbc_y1; /* blitter, src ury */
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u_int32_t fbc_pad5[2];
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u_int32_t fbc_x2; /* blitter, dst llx */
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u_int32_t fbc_y2; /* blitter, dst lly */
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u_int32_t fbc_pad6[2];
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u_int32_t fbc_x3; /* blitter, dst urx */
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u_int32_t fbc_y3; /* blitter, dst ury */
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u_int32_t fbc_pad7[2];
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u_int32_t fbc_offx; /* x offset for drawing */
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u_int32_t fbc_offy; /* y offset for drawing */
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u_int32_t fbc_pad8[2];
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u_int32_t fbc_incx; /* x offset for drawing */
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u_int32_t fbc_incy; /* y offset for drawing */
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u_int32_t fbc_pad81[2];
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u_int32_t fbc_clipminx; /* clip rectangle llx */
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u_int32_t fbc_clipminy; /* clip rectangle lly */
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u_int32_t fbc_pad9[2];
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u_int32_t fbc_clipmaxx; /* clip rectangle urx */
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u_int32_t fbc_clipmaxy; /* clip rectangle ury */
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u_int32_t fbc_pad10[2];
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u_int32_t fbc_fg; /* fg value for rop */
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u_int32_t fbc_bg;
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u_int32_t fbc_alu; /* operation to be performed */
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u_int32_t fbc_pad12[509];
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u_int32_t fbc_arectx; /* rectangle drawing, x coord */
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u_int32_t fbc_arecty; /* rectangle drawing, y coord */
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/* actually much more, but nothing more we need */
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};
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#if _CG6_LAYOUT_NOT_USED_ANYMORE
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/*
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* This structure exists only to compute the layout of the CG6
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* hardware. Each of the individual substructures lives on a
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* separate `page' (where a `page' is at least 4K), and many are
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* very far apart. We avoid large offsets (which make for lousy
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* code) by using pointers to the individual interesting pieces,
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* and map them in independently (to avoid using up PTEs unnecessarily).
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*/
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struct cg6_layout {
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/* ROM at 0 */
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union {
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int un_id; /* ID = ?? */
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char un_rom[65536]; /* 64K rom */
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char un_pad[0x200000];
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} cg6_rom_un;
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/* Brooktree DAC at 0x200000 */
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union {
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struct bt_regs un_btregs;
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char un_pad[0x040000];
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} cg6_bt_un;
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/* DHC, whatever that is, at 0x240000 */
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union {
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char un_pad[0x40000];
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} cg6_dhc_un;
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/* ALT, whatever that is, at 0x280000 */
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union {
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char un_pad[0x80000];
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} cg6_alt_un;
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/* FHC register at 0x300000 */
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union {
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int un_fhc;
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char un_pad[0x1000];
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} cg6_fhc_un;
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/* THC at 0x301000 */
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union {
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struct cg6_thc un_thc;
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char un_pad[0x400000 - 0x1000];
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} cg6_thc_un;
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/* FBC at 0x700000 */
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union {
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char un_pad[0x1000];
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} cg6_fbc_un;
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/* TEC at 0x701000 */
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union {
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char un_pad[0x100000 - 0x1000];
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struct cg6_tec_xxx un_tec;
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} cg6_tec_un;
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/* Video RAM at 0x800000 */
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char cg6_ram[1024 * 1024]; /* approx.? */
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};
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#endif
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