387 lines
12 KiB
C
387 lines
12 KiB
C
/* $NetBSD: frame.h,v 1.23 2009/01/18 01:19:33 bjh21 Exp $ */
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/*
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* Copyright (c) 1994-1997 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* frame.h
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*
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* Stack frames structures
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*
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* Created : 30/09/94
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*/
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#ifndef _ARM32_FRAME_H_
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#define _ARM32_FRAME_H_
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#include <arm/frame.h> /* Common ARM stack frames */
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#ifndef _LOCORE
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/*
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* System stack frames.
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*/
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typedef struct irqframe {
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unsigned int if_spsr;
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unsigned int if_r0;
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unsigned int if_r1;
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unsigned int if_r2;
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unsigned int if_r3;
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unsigned int if_r4;
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unsigned int if_r5;
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unsigned int if_r6;
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unsigned int if_r7;
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unsigned int if_r8;
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unsigned int if_r9;
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unsigned int if_r10;
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unsigned int if_r11;
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unsigned int if_r12;
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unsigned int if_usr_sp;
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unsigned int if_usr_lr;
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unsigned int if_svc_sp;
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unsigned int if_svc_lr;
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unsigned int if_pc;
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} irqframe_t;
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struct clockframe {
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struct irqframe cf_if;
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};
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/*
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* Switch frame.
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*
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* Should be a multiple of 8 bytes for dumpsys.
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*/
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struct switchframe {
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u_int sf_r4;
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u_int sf_r5;
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u_int sf_r6;
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u_int sf_r7;
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u_int sf_sp;
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u_int sf_pc;
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};
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/*
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* Stack frame. Used during stack traces (db_trace.c)
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*/
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struct frame {
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u_int fr_fp;
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u_int fr_sp;
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u_int fr_lr;
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u_int fr_pc;
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};
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#ifdef _KERNEL
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void validate_trapframe(trapframe_t *, int);
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#endif /* _KERNEL */
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#else /* _LOCORE */
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#include "opt_compat_netbsd.h"
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#include "opt_execfmt.h"
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#include "opt_multiprocessor.h"
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#include "opt_cpuoptions.h"
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#include "opt_arm_debug.h"
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#include <machine/cpu.h>
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/*
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* This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process
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* any pending softints.
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*/
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#ifdef __HAVE_FAST_SOFTINTS
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#define DO_PENDING_SOFTINTS \
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ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\
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teq r0, #0 /* Test for 0. */ ;\
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bne 10f /* skip softints if != 0 */ ;\
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ldr r0, [r4, #CI_CPL] /* Get current priority level */;\
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ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\
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movs r0, r1, lsr r0 /* shift mask by cpl */ ;\
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blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\
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10:
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#else
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#define DO_PENDING_SOFTINTS /* nothing */
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#endif
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/*
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* AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS
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* These are used in order to support dynamic enabling/disabling of
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* alignment faults when executing old a.out ARM binaries.
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*
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* Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain
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* pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
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* relies on r4 being preserved.
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*/
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#ifdef EXEC_AOUT
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#define AST_ALIGNMENT_FAULT_LOCALS \
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.Laflt_cpufuncs: ;\
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.word _C_LABEL(cpufuncs)
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/*
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* This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at
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* the top of interrupt/exception handlers.
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*
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* When invoked, r0 *must* contain the value of SPSR on the current
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* trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS
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* is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME.
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*/
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#define ENABLE_ALIGNMENT_FAULTS \
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
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teq r0, #(PSR_USR32_MODE) ;\
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GET_CURCPU(r4) /* r4 = cpuinfo */ ;\
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bne 1f /* Not USR mode skip AFLT */ ;\
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ldr r1, [r4, #CI_CURPCB] /* get curpcb from cpu_info */ ;\
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ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
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tst r1, #PCB_NOALIGNFLT ;\
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beq 1f /* AFLTs already enabled */ ;\
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ldr r2, .Laflt_cpufuncs ;\
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ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
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mov r0, #-1 ;\
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mov lr, pc ;\
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ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
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1:
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/*
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* This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or
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* PULLFRAME at the end of interrupt/exception handlers. We know that
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* r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did
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* for use.
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*/
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#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
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DO_PENDING_SOFTINTS ;\
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ldr r0, [sp] /* Get the SPSR from stack */ ;\
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mrs r5, cpsr /* save CPSR */ ;\
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orr r1, r5, #(IF32_bits) ;\
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msr cpsr_c, r1 /* Disable interrupts */ ;\
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and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
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teq r0, #(PSR_USR32_MODE) ;\
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bne 3f /* Nope, get out now */ ;\
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1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\
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teq r1, #0x00000000 ;\
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bne 2f /* Yup. Go deal with it */ ;\
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ldr r1, [r4, #CI_CURPCB] /* Get current PCB */ ;\
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ldr r0, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
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tst r0, #PCB_NOALIGNFLT ;\
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beq 3f /* Keep AFLTs enabled */ ;\
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ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
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ldr r2, .Laflt_cpufuncs ;\
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mov r0, #-1 ;\
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bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\
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adr lr, 3f ;\
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ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\
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/* NOTREACHED */ \
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2: mov r1, #0x00000000 ;\
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str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\
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bic r5, r5, #(IF32_bits) ;\
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msr cpsr_c, r5 /* Restore interrupts */ ;\
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mov r0, sp ;\
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bl _C_LABEL(ast) /* ast(frame) */ ;\
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orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\
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msr cpsr_c, r0 ;\
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b 1b /* Back around again */ ;\
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3:
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#else /* !EXEC_AOUT */
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#define AST_ALIGNMENT_FAULT_LOCALS
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#define ENABLE_ALIGNMENT_FAULTS GET_CURCPU(r4)
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#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
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DO_PENDING_SOFTINTS ;\
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ldr r0, [sp] /* Get the SPSR from stack */ ;\
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mrs r5, cpsr /* save CPSR */ ;\
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orr r1, r5, #(IF32_bits) ;\
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msr cpsr_c, r1 /* Disable interrupts */ ;\
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and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
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teq r0, #(PSR_USR32_MODE) ;\
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bne 2f /* Nope, get out now */ ;\
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1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\
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teq r1, #0x00000000 ;\
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beq 2f /* Nope. Just bail */ ;\
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mov r1, #0x00000000 ;\
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str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\
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bic r5, r5, #(IF32_bits) ;\
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msr cpsr_c, r5 /* Restore interrupts */ ;\
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mov r0, sp ;\
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bl _C_LABEL(ast) /* ast(frame) */ ;\
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orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\
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msr cpsr_c, r0 ;\
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b 1b ;\
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2:
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#endif /* EXEC_AOUT */
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#ifdef ARM_LOCK_CAS_DEBUG
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#define LOCK_CAS_DEBUG_LOCALS \
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.L_lock_cas_restart: ;\
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.word _C_LABEL(_lock_cas_restart)
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#if defined(__ARMEB__)
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#define LOCK_CAS_DEBUG_COUNT_RESTART \
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ble 99f ;\
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ldr r0, .L_lock_cas_restart ;\
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ldmia r0, {r1-r2} /* load ev_count */ ;\
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adds r2, r2, #1 /* 64-bit incr (lo) */ ;\
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adc r1, r1, #0 /* 64-bit incr (hi) */ ;\
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stmia r0, {r1-r2} /* store ev_count */
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#else /* __ARMEB__ */
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#define LOCK_CAS_DEBUG_COUNT_RESTART \
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ble 99f ;\
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ldr r0, .L_lock_cas_restart ;\
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ldmia r0, {r1-r2} /* load ev_count */ ;\
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adds r1, r1, #1 /* 64-bit incr (lo) */ ;\
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adc r2, r2, #0 /* 64-bit incr (hi) */ ;\
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stmia r0, {r1-r2} /* store ev_count */
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#endif /* __ARMEB__ */
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#else /* ARM_LOCK_CAS_DEBUG */
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#define LOCK_CAS_DEBUG_LOCALS /* nothing */
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#define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */
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#endif /* ARM_LOCK_CAS_DEBUG */
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#define LOCK_CAS_CHECK_LOCALS \
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.L_lock_cas: ;\
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.word _C_LABEL(_lock_cas) ;\
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.L_lock_cas_end: ;\
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.word _C_LABEL(_lock_cas_end) ;\
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LOCK_CAS_DEBUG_LOCALS
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#define LOCK_CAS_CHECK \
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ldr r0, [sp] /* get saved PSR */ ;\
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and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\
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teq r0, #(PSR_SVC32_MODE) ;\
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bne 99f /* nope, get out now */ ;\
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ldr r0, [sp, #(IF_PC)] ;\
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ldr r1, .L_lock_cas_end ;\
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cmp r0, r1 ;\
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bge 99f ;\
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ldr r1, .L_lock_cas ;\
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cmp r0, r1 ;\
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strgt r1, [sp, #(IF_PC)] ;\
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LOCK_CAS_DEBUG_COUNT_RESTART ;\
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99:
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/*
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* ASM macros for pushing and pulling trapframes from the stack
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*
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* These macros are used to handle the irqframe and trapframe structures
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* defined above.
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*/
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/*
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* PUSHFRAME - macro to push a trap frame on the stack in the current mode
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* Since the current mode is used, the SVC lr field is not defined.
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*
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* NOTE: r13 and r14 are stored separately as a work around for the
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* SA110 rev 2 STM^ bug
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*/
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#define PUSHFRAME \
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str lr, [sp, #-4]!; /* Push the return address */ \
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sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
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stmia sp, {r0-r12}; /* Push the user mode registers */ \
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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mrs r0, spsr_all; /* Put the SPSR on the stack */ \
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str r0, [sp, #-4]!
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/*
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* PULLFRAME - macro to pull a trap frame from the stack in the current mode
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* Since the current mode is used, the SVC lr field is ignored.
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*/
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#define PULLFRAME \
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ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
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msr spsr_all, r0; \
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ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
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mov r0, r0; /* NOP for previous instruction */ \
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add sp, sp, #(4*17); /* Adjust the stack pointer */ \
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ldr lr, [sp], #0x0004 /* Pull the return address */
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/*
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* PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
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* This should only be used if the processor is not currently in SVC32
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* mode. The processor mode is switched to SVC mode and the trap frame is
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* stored. The SVC lr field is used to store the previous value of
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* lr in SVC mode.
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*
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* NOTE: r13 and r14 are stored separately as a work around for the
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* SA110 rev 2 STM^ bug
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*/
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#define PUSHFRAMEINSVC \
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stmdb sp, {r0-r3}; /* Save 4 registers */ \
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mov r0, lr; /* Save xxx32 r14 */ \
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mov r1, sp; /* Save xxx32 sp */ \
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mrs r3, spsr; /* Save xxx32 spsr */ \
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mrs r2, cpsr; /* Get the CPSR */ \
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bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
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orr r2, r2, #(PSR_SVC32_MODE); \
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msr cpsr_c, r2; /* Punch into SVC mode */ \
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mov r2, sp; /* Save SVC sp */ \
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str r0, [sp, #-4]!; /* Push return address */ \
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str lr, [sp, #-4]!; /* Push SVC lr */ \
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str r2, [sp, #-4]!; /* Push SVC sp */ \
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msr spsr_all, r3; /* Restore correct spsr */ \
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ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
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sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
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stmia sp, {r0-r12}; /* Push the user mode registers */ \
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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mrs r0, spsr_all; /* Put the SPSR on the stack */ \
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str r0, [sp, #-4]!
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/*
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* PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
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* in SVC32 mode and restore the saved processor mode and PC.
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* This should be used when the SVC lr register needs to be restored on
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* exit.
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*/
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#define PULLFRAMEFROMSVCANDEXIT \
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ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
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msr spsr_all, r0; /* restore SPSR */ \
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ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
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mov r0, r0; /* NOP for previous instruction */ \
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add sp, sp, #(4*15); /* Adjust the stack pointer */ \
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ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
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#endif /* _LOCORE */
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#endif /* _ARM32_FRAME_H_ */
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