465 lines
12 KiB
C
465 lines
12 KiB
C
/* $NetBSD: au_icu.c,v 1.21 2006/12/21 15:55:23 yamt Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Itronix Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Interrupt support for the Alchemy Semiconductor Au1x00 CPUs.
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*
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* The Alchemy Semiconductor Au1x00's interrupts are wired to two internal
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* interrupt controllers.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.21 2006/12/21 15:55:23 yamt Exp $");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/queue.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <mips/locore.h>
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#include <mips/alchemy/include/aureg.h>
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#include <mips/alchemy/include/auvar.h>
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#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
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/*
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* This is a mask of bits to clear in the SR when we go to a
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* given hardware interrupt priority level.
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*/
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const uint32_t ipl_sr_bits[_IPL_N] = {
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0, /* 0: IPL_NONE */
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MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */
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MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTCLOCK */
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MIPS_SOFT_INT_MASK_0, /* 3: IPL_SOFTNET */
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MIPS_SOFT_INT_MASK_0, /* 4: IPL_SOFTSERIAL */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_0, /* 5: IPL_BIO */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_0, /* 6: IPL_NET */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_0, /* 7: IPL_{SERIAL,TTY} */
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MIPS_SOFT_INT_MASK_0|
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MIPS_SOFT_INT_MASK_1|
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MIPS_INT_MASK_0|
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MIPS_INT_MASK_1|
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MIPS_INT_MASK_2|
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MIPS_INT_MASK_3|
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MIPS_INT_MASK_4|
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MIPS_INT_MASK_5, /* 8: IPL_{CLOCK,HIGH} */
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};
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/*
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* This is a mask of bits to clear in the SR when we go to a
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* given software interrupt priority level.
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* Hardware ipls are port/board specific.
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*/
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const uint32_t mips_ipl_si_to_sr[SI_NQUEUES] = {
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[SI_SOFT] = MIPS_SOFT_INT_MASK_0,
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[SI_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
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[SI_SOFTNET] = MIPS_SOFT_INT_MASK_0,
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[SI_SOFTSERIAL] = MIPS_SOFT_INT_MASK_0,
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};
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#define NIRQS 64
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struct au_icu_intrhead {
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struct evcnt intr_count;
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int intr_refcnt;
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};
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struct au_icu_intrhead au_icu_intrtab[NIRQS];
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#define NINTRS 4 /* MIPS INT0 - INT3 */
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struct au_intrhand {
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LIST_ENTRY(au_intrhand) ih_q;
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int (*ih_func)(void *);
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void *ih_arg;
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int ih_irq;
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int ih_mask;
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};
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struct au_cpuintr {
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LIST_HEAD(, au_intrhand) cintr_list;
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struct evcnt cintr_count;
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};
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struct au_cpuintr au_cpuintrs[NINTRS];
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const char *au_cpuintrnames[NINTRS] = {
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"icu 0, req 0",
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"icu 0, req 1",
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"icu 1, req 0",
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"icu 1, req 1",
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};
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static bus_addr_t ic0_base, ic1_base;
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void
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au_intr_init(void)
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{
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int i;
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struct au_chipdep *chip;
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for (i = 0; i < NINTRS; i++) {
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LIST_INIT(&au_cpuintrs[i].cintr_list);
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evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count,
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EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]);
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}
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chip = au_chipdep();
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KASSERT(chip != NULL);
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ic0_base = chip->icus[0];
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ic1_base = chip->icus[1];
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for (i = 0; i < NIRQS; i++) {
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au_icu_intrtab[i].intr_refcnt = 0;
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evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count,
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EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]);
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}
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/* start with all interrupts masked */
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REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff;
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REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff;
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REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff;
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REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff;
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REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff;
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REGVAL(ic0_base + IC_TEST_BIT) = 0;
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REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff;
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REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff;
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REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff;
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REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff;
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REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff;
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REGVAL(ic1_base + IC_TEST_BIT) = 0;
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}
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void *
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au_intr_establish(int irq, int req, int level, int type,
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int (*func)(void *), void *arg)
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{
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struct au_intrhand *ih;
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uint32_t icu_base;
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int cpu_int, s;
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struct au_chipdep *chip;
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chip = au_chipdep();
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KASSERT(chip != NULL);
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if (irq >= NIRQS)
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panic("au_intr_establish: bogus IRQ %d", irq);
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if (req > 1)
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panic("au_intr_establish: bogus request %d", req);
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ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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return (NULL);
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ih->ih_func = func;
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ih->ih_arg = arg;
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ih->ih_irq = irq;
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ih->ih_mask = (1 << (irq & 31));
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s = splhigh();
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/*
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* First, link it into the tables.
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* XXX do we want a separate list (really, should only be one item, not
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* a list anyway) per irq, not per CPU interrupt?
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*/
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cpu_int = (irq < 32 ? 0 : 2) + req;
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LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q);
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/*
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* Now enable it.
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*/
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if (au_icu_intrtab[irq].intr_refcnt++ == 0) {
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icu_base = (irq < 32) ? ic0_base : ic1_base;
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irq &= 31; /* throw away high bit if set */
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irq = 1 << irq; /* only used as a mask from here on */
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/* XXX Only level interrupts for now */
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switch (type) {
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case IST_NONE:
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case IST_PULSE:
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case IST_EDGE:
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panic("unsupported irq type %d", type);
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/* NOTREACHED */
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case IST_LEVEL:
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case IST_LEVEL_HIGH:
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REGVAL(icu_base + IC_CONFIG2_SET) = irq;
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REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
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REGVAL(icu_base + IC_CONFIG0_SET) = irq;
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break;
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case IST_LEVEL_LOW:
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REGVAL(icu_base + IC_CONFIG2_SET) = irq;
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REGVAL(icu_base + IC_CONFIG1_SET) = irq;
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REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
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break;
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}
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wbflush();
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/* XXX handle GPIO interrupts - not done at all yet */
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if (cpu_int & 0x1)
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REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq;
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else
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REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq;
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/* Associate interrupt with peripheral */
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REGVAL(icu_base + IC_SOURCE_SET) = irq;
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/* Actually enable the interrupt */
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REGVAL(icu_base + IC_MASK_SET) = irq;
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/* And allow the interrupt to interrupt idle */
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REGVAL(icu_base + IC_WAKEUP_SET) = irq;
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wbflush();
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}
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splx(s);
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return (ih);
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}
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void
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au_intr_disestablish(void *cookie)
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{
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struct au_intrhand *ih = cookie;
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uint32_t icu_base;
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int irq, s;
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irq = ih->ih_irq;
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s = splhigh();
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/*
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* First, remove it from the table.
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*/
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LIST_REMOVE(ih, ih_q);
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/*
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* Now, disable it, if there is nothing remaining on the
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* list.
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*/
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if (au_icu_intrtab[irq].intr_refcnt-- == 1) {
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icu_base = (irq < 32) ? ic0_base : ic1_base;
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irq &= 31; /* throw away high bit if set */
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irq = 1 << irq; /* only used as a mask from here on */
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REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq;
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REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
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REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
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/* disable with MASK_CLEAR and WAKEUP_CLEAR */
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REGVAL(icu_base + IC_MASK_CLEAR) = irq;
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REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq;
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wbflush();
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}
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splx(s);
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free(ih, M_DEVBUF);
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}
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void
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au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
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{
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struct au_intrhand *ih;
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int level;
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uint32_t icu_base, irqstat, irqmask;
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icu_base = irqstat = 0;
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for (level = 3; level >= 0; level--) {
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if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
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continue;
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/*
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* XXX the following may well be slow to execute.
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* investigate and possibly speed up.
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*
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* is something like:
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*
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* irqstat = REGVAL(
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* (level & 4 == 0) ? IC0_BASE ? IC1_BASE +
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* (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT);
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*
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* be any better?
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*
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*/
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switch (level) {
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case 0:
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icu_base = ic0_base;
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irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
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break;
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case 1:
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icu_base = ic0_base;
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irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
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break;
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case 2:
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icu_base = ic1_base;
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irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
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break;
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case 3:
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icu_base = ic1_base;
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irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
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break;
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}
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irqmask = REGVAL(icu_base + IC_MASK_READ);
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au_cpuintrs[level].cintr_count.ev_count++;
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LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) {
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int mask = ih->ih_mask;
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if (mask & irqmask & irqstat) {
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au_icu_intrtab[ih->ih_irq].intr_count.ev_count++;
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(*ih->ih_func)(ih->ih_arg);
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if (REGVAL(icu_base + IC_MASK_READ) & mask) {
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REGVAL(icu_base + IC_MASK_CLEAR) = mask;
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REGVAL(icu_base + IC_MASK_SET) = mask;
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wbflush();
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}
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}
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}
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cause &= ~(MIPS_INT_MASK_0 << level);
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}
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/* Re-enable anything that we have processed. */
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_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
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}
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/*
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* Some devices (e.g. PCMCIA) want to be able to mask interrupts at
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* the ICU, and leave them masked off until some later time
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* (e.g. reenabled by a soft interrupt).
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*/
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void
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au_intr_enable(int irq)
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{
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int s;
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uint32_t icu_base, mask;
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if (irq >= NIRQS)
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panic("au_intr_enable: bogus IRQ %d", irq);
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icu_base = (irq < 32) ? ic0_base : ic1_base;
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mask = irq & 31;
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mask = 1 << mask;
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s = splhigh();
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/* only enable the interrupt if we have a handler */
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if (au_icu_intrtab[irq].intr_refcnt) {
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REGVAL(icu_base + IC_MASK_SET) = mask;
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REGVAL(icu_base + IC_WAKEUP_SET) = mask;
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wbflush();
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}
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splx(s);
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}
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void
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au_intr_disable(int irq)
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{
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int s;
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uint32_t icu_base, mask;
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if (irq >= NIRQS)
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panic("au_intr_disable: bogus IRQ %d", irq);
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icu_base = (irq < 32) ? ic0_base : ic1_base;
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mask = irq & 31;
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mask = 1 << mask;
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s = splhigh();
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REGVAL(icu_base + IC_MASK_CLEAR) = mask;
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REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask;
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wbflush();
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splx(s);
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}
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