331 lines
7.9 KiB
ArmAsm
331 lines
7.9 KiB
ArmAsm
/* $NetBSD: netwalker_start.S,v 1.5 2014/05/06 11:22:53 hkenken Exp $ */
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/*-
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* Copyright (c) 2009 SHIMIZU Ryo <ryo@nerv.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2002, 2003, 2010 Genetec Corporation. All rights reserved.
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* Written by Kenichi Hashimoto and Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_imx.h"
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#include "opt_com.h"
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#include "opt_cpuoptions.h"
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#include "opt_cputypes.h"
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#include "opt_arm_debug.h"
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#include <arm/asm.h>
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#include <arm/armreg.h>
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#include "assym.h"
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#include <arm/imx/imx51reg.h>
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#include <arm/imx/imxuartreg.h>
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#include <evbarm/netwalker/netwalker_reg.h>
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RCSID("$NetBSD: netwalker_start.S,v 1.5 2014/05/06 11:22:53 hkenken Exp $")
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#if defined(VERBOSE_INIT_ARM)
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#define DEBUG_STARTUP
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#define XPUTC(n) mov r0, n; bl _C_LABEL(debugputc)
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#else
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#define XPUTC(n)
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#endif
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#ifndef SDRAM_START
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#define SDRAM_START CSD0DDR_BASE
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#endif
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#define KERNEL_TEXT_ADDR (SDRAM_START+0x00100000)
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#define INIT_MEMSIZE 128
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#define TEMP_L1_TABLE (SDRAM_START + INIT_MEMSIZE * 0x100000 - L1_TABLE_SIZE)
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#ifdef DEBUG_STARTUP
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#define CHECKPOINT(n) CHECKPOINT2(n,r0,r1)
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#define CHECKPOINT2(n,ra,rb) \
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mov ra,#0x30+(n); \
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ldr rb, =UART1_BASE; \
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str ra, [rb, #IMX_UTXD]
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#else
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#define CHECKPOINT(n) /* nothing to do */
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#define CHECKPOINT2(n,ra,rb) /* nothing to do */
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#endif
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.section .start,"ax",%progbits
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.text
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.global _C_LABEL(netwalker_start)
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_C_LABEL(netwalker_start):
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CHECKPOINT(0)
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#ifdef DEBUG_STARTUP
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ldr sp,=SDRAM_START+0x4000
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bl newline
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ldr r0, =0xdeadb01f
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bl _C_LABEL(debugprintx)
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bl newline
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mov r0, pc
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bl _C_LABEL(debugprintx)
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bl newline
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mrc p15, 0, r0, c0, c0, 3 /* read TLB type register */
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bl _C_LABEL(debugprintx)
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bl newline
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mrc p15, 0, r0, c1, c0, 0 /* read control register */
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bl _C_LABEL(debugprintx)
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bl newline
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mrc p15, 0, r0, c2, c0, 0 /* read TTB0 */
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bl _C_LABEL(debugprintx)
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bl newline
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mrc p15, 0, r0, c2, c0, 1 /* read TTB1 */
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bl _C_LABEL(debugprintx)
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bl newline
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ldr r0, =0xbabeface
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bl _C_LABEL(debugprintx)
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bl newline
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/* dump some of UART1 registers to know clock frequency */
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ldr r4,=UART1_BASE
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ldr r0,[r4,#IMX_UBMR]
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bl _C_LABEL(debugprintx)
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bl newline
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ldr r0,[r4,#IMX_UBIR]
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bl _C_LABEL(debugprintx)
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bl newline
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ldr r0,[r4,#IMX_UFCR]
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bl _C_LABEL(debugprintx)
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bl newline
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#endif /* DEBUG_STARTUP */
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/* Are we running on right place ? */
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ldr r2, =KERNEL_TEXT_ADDR
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adr r0, _C_LABEL(netwalker_start)
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cmp r0, r2
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beq relocated
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/*
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* move me to RAM
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*/
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ldr r1, .Lcopy_size
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add r1, r1, #3
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mov r1, r1, LSR #2
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mov r4, r2
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bhs 5f
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/* src < dest. copy from top */
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add r0,r0,r1,LSL #2
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add r2,r2,r1,LSL #2
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3: ldr r3,[r0,#-4]!
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str r3,[r2,#-4]!
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subs r1,r1,#1
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bhi 3b
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b 7f
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/* src >= dest. copy from bottom */
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5: ldr r3,[r0],#4
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str r3,[r2],#4
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subs r1,r1,#1
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bhi 5b
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7:
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/*
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* Okay, we are finished relocating the text segment. Now
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* we need to leap to the next instruction.
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*/
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ldr r0, .Lrelocate_address
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ldr r1, .Lrelocate_offset
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add pc, r0, r1
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.Lrelocate_offset: .word relocated-_C_LABEL(netwalker_start)
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relocated:
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CHECKPOINT(1)
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/* Move into supervisor mode and disable IRQs/FIQs. */
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cpsid if, #PSR_SVC32_MODE
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bl cortex_init
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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adr r1, .Lmmu_init_table
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bl arm_boot_l1pt_init
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CHECKPOINT(2)
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/*
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* Turn on the MMU, Caches, etc.
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*/
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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bl arm_cpuinit
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CHECKPOINT(3)
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movw ip, #:lower16:start
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movt ip, #:upper16:start
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bx ip /* Jump to start (flushes pipeline). */
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/* NOTREACHED */
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/*
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* Calculate size of kernel to copy. Don't bother to copy bss,
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* although I guess the CPU could use the warmup exercise ...
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*/
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.Lcopy_size:
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.word _edata - _C_LABEL(netwalker_start)
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.Lrelocate_address:
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.word KERNEL_BASE_phys
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#include <arm/cortex/a9_mpsubr.S>
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.Lmmu_init_table:
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/* fill all table VA==PA */
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MMU_INIT(0x00000000, 0x00000000, 1 << (32 - L1_S_SHIFT),
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L1_S_PROTO_armv7 | L1_S_APv7_KRW)
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/* Map memory 1:1 VA to PA, write-back cacheable, shareable */
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MMU_INIT(SDRAM_START, SDRAM_START, 512,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
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/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
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MMU_INIT(KERNEL_BASE, SDRAM_START, INIT_MEMSIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
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/*
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* In case of early start debugging it might be useful to map
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* SoC registers (for UART access).
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*/
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MMU_INIT(NETWALKER_IO_VBASE0, NETWALKER_IO_PBASE0, 4,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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#ifdef DEBUG_STARTUP
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.Luart0adr:
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.word UART1_BASE
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.global _C_LABEL(debugprintx)
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_C_LABEL(debugprintx):
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stmfd sp!, {r0, r3, lr}
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mov r3, r0
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mov r0, #'0'
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bl debugputc
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mov r0, #'x'
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bl debugputc
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bl print_r3
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ldmfd sp!, {r0, r3, pc}
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.global _C_LABEL(debugprint)
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_C_LABEL(debugprint):
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stmfd sp!, {r0, r1, lr}
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mov r1, r0
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1:
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ldrb r0, [r1], #1
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cmp r0, #0
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beq 9f
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bl debugputc
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b 1b
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9:
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ldmfd sp!, {r0, r1, pc}
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print_r3:
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stmfd sp!, {r0, r3-r6, lr}
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mov r4, #28
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mov r5, #0xf
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1:
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and r6, r5, r3, ROR r4
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cmp r6, #10
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addlt r0, r6, #'0'
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addge r0, r6, #('a' - 0x0a)
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bl debugputc
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subs r4, r4, #4
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bge 1b
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ldmfd sp!, {r0, r3-r6, pc}
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.global _C_LABEL(debugputc)
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_C_LABEL(debugputc):
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stmfd sp!, {r0, r1, r2, lr}
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ldr r1, .Luart0adr
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1: /* wait */
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ldr r2, [r1, #0x98]
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tst r2, #0x4000
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beq 1b
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/* output */
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strb r0, [r1, #0x40]
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ldmfd sp!, {r0, r1, r2, pc}
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newline:
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mov r1, lr
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mov r0, #0x0d
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bl _C_LABEL(debugputc)
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mov lr, r1
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mov r0, #0x0a
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b _C_LABEL(debugputc)
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#endif /* DEBUG_STARTUP */
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END(_C_LABEL(netwalker_start))
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