88 lines
3.5 KiB
C
88 lines
3.5 KiB
C
/* $NetBSD: si4136reg.h,v 1.4 2006/03/08 08:26:50 dyoung Exp $ */
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/*
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* Copyright (c) 2005 David Young. All rights reserved.
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*
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* This code was written by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
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* Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_SI4136REG_H_
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#define _DEV_IC_SI4136REG_H_
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/*
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* Serial bus format for Silicon Laboratories Si4126/Si4136 RF synthesizer.
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*/
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#define SI4126_TWI_DATA_MASK __BITS(21, 4)
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#define SI4126_TWI_ADDR_MASK __BITS(3, 0)
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/*
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* Registers for Silicon Laboratories Si4126/Si4136 RF synthesizer.
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*/
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#define SI4126_MAIN 0 /* main configuration */
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#define SI4126_MAIN_AUXSEL_MASK __BITS(13, 12) /* aux. output pin function */
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/* reserved */
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#define SI4126_MAIN_AUXSEL_RSVD SHIFTIN(0x0, SI4126_MAIN_AUXSEL_MASK)
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/* force low */
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#define SI4126_MAIN_AUXSEL_FRCLOW SHIFTIN(0x1, SI4126_MAIN_AUXSEL_MASK)
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/* Lock Detect (LDETB) */
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#define SI4126_MAIN_AUXSEL_LDETB SHIFTIN(0x3, SI4126_MAIN_AUXSEL_MASK)
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#define SI4126_MAIN_IFDIV_MASK __BITS(11, 10) /* IFOUT = IFVCO
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* frequency / 2**IFDIV.
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*/
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/* 1: divide crystal input (XIN) by 2 */
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#define SI4126_MAIN_XINDIV2 __BIT(6)
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#define SI4126_MAIN_LPWR __BIT(5) /* 1: low-power mode */
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#define SI4126_MAIN_AUTOPDB __BIT(3) /* 1: equivalent to
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* reg[SI4126_POWER] <-
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* SI4126_POWER_PDIB |
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* SI4126_POWER_PDRB.
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*
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* 0: power-down under control
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* of reg[SI4126_POWER].
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*/
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#define SI4126_GAIN 1 /* phase detector gain */
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#define SI4126_GAIN_KPI_MASK __BITS(5, 4) /* IF phase detector gain */
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#define SI4126_GAIN_KP2_MASK __BITS(3, 2) /* RF2 phase detector gain */
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#define SI4126_GAIN_KP1_MASK __BITS(1, 0) /* RF1 phase detector gain */
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#define SI4126_POWER 2 /* powerdown */
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#define SI4126_POWER_PDIB __BIT(1) /* 1: IF synthesizer on */
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#define SI4126_POWER_PDRB __BIT(0) /* 1: RF synthesizer on */
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#define SI4126_RF1N 3 /* RF1 N divider */
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#define SI4126_RF2N 4 /* RF2 N divider */
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#define SI4126_IFN 5 /* IF N divider */
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#define SI4126_RF1R 6 /* RF1 R divider */
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#define SI4126_RF2R 7 /* RF2 R divider */
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#define SI4126_IFR 8 /* IF R divider */
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#endif /* _DEV_IC_SI4136REG_H_ */
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