413 lines
11 KiB
C
413 lines
11 KiB
C
/* $NetBSD: pci_550.c,v 1.12 1998/08/01 20:25:12 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center, and by Andrew Gallatin.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.12 1998/08/01 20:25:12 thorpej Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/syslog.h>
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#include <vm/vm.h>
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#include <machine/autoconf.h>
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#include <machine/rpb.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <alpha/pci/ciareg.h>
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#include <alpha/pci/ciavar.h>
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#include <alpha/pci/pci_550.h>
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#ifndef EVCNT_COUNTERS
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#include <machine/intrcnt.h>
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#endif
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#include "sio.h"
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#if NSIO
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#include <alpha/pci/siovar.h>
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#endif
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int dec_550_intr_map __P((void *, pcitag_t, int, int,
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pci_intr_handle_t *));
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const char *dec_550_intr_string __P((void *, pci_intr_handle_t));
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void *dec_550_intr_establish __P((void *, pci_intr_handle_t,
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int, int (*func)(void *), void *));
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void dec_550_intr_disestablish __P((void *, void *));
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void *dec_550_pciide_compat_intr_establish __P((void *, struct device *,
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struct pci_attach_args *, int, int (*)(void *), void *));
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#define DEC_550_PCI_IRQ_BEGIN 8
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#define DEC_550_MAX_IRQ 48
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/*
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* The Miata has a Pyxis, which seems to have problems with stray
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* interrupts. Work around this by just ignoring strays.
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*/
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#define PCI_STRAY_MAX 0
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struct alpha_shared_intr *dec_550_pci_intr;
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#ifdef EVCNT_COUNTERS
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struct evcnt dec_550_intr_evcnt;
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#endif
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void dec_550_iointr __P((void *framep, unsigned long vec));
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void dec_550_intr_enable __P((int irq));
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void dec_550_intr_disable __P((int irq));
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void
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pci_550_pickintr(ccp)
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struct cia_config *ccp;
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{
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bus_space_tag_t iot = &ccp->cc_iot;
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pci_chipset_tag_t pc = &ccp->cc_pc;
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int i;
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pc->pc_intr_v = ccp;
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pc->pc_intr_map = dec_550_intr_map;
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pc->pc_intr_string = dec_550_intr_string;
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pc->pc_intr_establish = dec_550_intr_establish;
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pc->pc_intr_disestablish = dec_550_intr_disestablish;
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pc->pc_pciide_compat_intr_establish =
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dec_550_pciide_compat_intr_establish;
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/*
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* DEC 550's interrupts are enabled via the Pyxis interrupt
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* mask register. Nothing to map.
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*/
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for (i = DEC_550_PCI_IRQ_BEGIN; i < DEC_550_MAX_IRQ; i++)
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dec_550_intr_disable(i);
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dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ);
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for (i = 0; i < DEC_550_MAX_IRQ; i++)
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alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i,
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PCI_STRAY_MAX);
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#if NSIO
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sio_intr_setup(pc, iot);
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#endif
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set_iointr(dec_550_iointr);
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}
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int
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dec_550_intr_map(ccv, bustag, buspin, line, ihp)
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void *ccv;
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pcitag_t bustag;
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int buspin, line;
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pci_intr_handle_t *ihp;
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{
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struct cia_config *ccp = ccv;
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pci_chipset_tag_t pc = &ccp->cc_pc;
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int bus, device, function;
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if (buspin == 0) {
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/* No IRQ used. */
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return 1;
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}
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if (buspin > 4) {
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printf("dec_550_intr_map: bad interrupt pin %d\n", buspin);
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return 1;
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}
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alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function);
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/*
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* There are two main variants of Miata: Miata 1 (Intel SIO)
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* and Miata {1.5,2} (Cypress).
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*
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* The Miata 1 has a CMD PCI IDE wired to compatibility mode at
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* device 4 of bus 0. This variant apparently also has the
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* Pyxis DMA bug.
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*
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* On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives
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* on device 7 of bus 0. This device has PCI IDE wired to
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* compatibility mode on functions 1 and 2.
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*
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* There will be no interrupt mapping for these devices, so just
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* bail out now.
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*/
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if (bus == 0) {
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if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
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/* Miata 1 */
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if (device == 7)
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panic("dec_550_intr_map: SIO device");
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else if (device == 4)
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return (1);
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} else {
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/* Miata 1.5 or Miata 2 */
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if (device == 7) {
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if (function == 0)
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panic("dec_550_intr_map: SIO device");
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return (1);
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}
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}
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}
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/*
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* The console places the interrupt mapping in the "line" value.
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* A value of (char)-1 indicates there is no mapping.
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*/
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if (line == 0xff) {
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printf("dec_550_intr_map: no mapping for %d/%d/%d\n",
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bus, device, function);
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return (1);
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}
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/* Account for the PCI interrupt offset. */
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line += DEC_550_PCI_IRQ_BEGIN;
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if (line >= DEC_550_MAX_IRQ)
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panic("dec_550_intr_map: dec 550 irq too large (%d)\n",
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line);
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*ihp = line;
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return (0);
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}
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const char *
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dec_550_intr_string(ccv, ih)
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void *ccv;
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pci_intr_handle_t ih;
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{
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#if 0
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struct cia_config *ccp = ccv;
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#endif
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static char irqstr[16]; /* 12 + 2 + NULL + sanity */
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if (ih >= DEC_550_MAX_IRQ)
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panic("dec_550_intr_string: bogus 550 IRQ 0x%x\n", ih);
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sprintf(irqstr, "dec 550 irq %d", ih);
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return (irqstr);
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}
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void *
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dec_550_intr_establish(ccv, ih, level, func, arg)
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void *ccv, *arg;
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pci_intr_handle_t ih;
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int level;
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int (*func) __P((void *));
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{
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#if 0
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struct cia_config *ccp = ccv;
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#endif
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void *cookie;
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if (ih >= DEC_550_MAX_IRQ)
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panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%x\n", ih);
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cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL,
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level, func, arg, "dec 550 irq");
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if (cookie != NULL && alpha_shared_intr_isactive(dec_550_pci_intr, ih))
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dec_550_intr_enable(ih);
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return (cookie);
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}
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void
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dec_550_intr_disestablish(ccv, cookie)
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void *ccv, *cookie;
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{
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#if 0
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struct cia_config *ccp = ccv;
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#endif
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struct alpha_shared_intrhand *ih = cookie;
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unsigned int irq = ih->ih_num;
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int s;
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s = splhigh();
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alpha_shared_intr_disestablish(dec_550_pci_intr, cookie,
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"dec 550 irq");
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if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) {
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dec_550_intr_disable(irq);
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alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq,
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IST_NONE);
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}
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splx(s);
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}
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void *
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dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg)
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void *v;
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struct device *dev;
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struct pci_attach_args *pa;
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int chan;
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int (*func) __P((void *));
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void *arg;
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{
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pci_chipset_tag_t pc = pa->pa_pc;
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void *cookie = NULL;
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int bus, irq;
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alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
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/*
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* If this isn't PCI bus #0, all bets are off.
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*/
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if (bus != 0)
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return (NULL);
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irq = PCIIDE_COMPAT_IRQ(chan);
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#if NSIO
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cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
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func, arg);
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#endif
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return (cookie);
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}
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void
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dec_550_iointr(framep, vec)
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void *framep;
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unsigned long vec;
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{
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int irq;
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if (vec >= 0x900) {
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irq = ((vec - 0x900) >> 4) + DEC_550_PCI_IRQ_BEGIN;
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if (irq >= DEC_550_MAX_IRQ)
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panic("550_iointr: vec 0x%x out of range\n", vec);
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#ifdef EVCNT_COUNTERS
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dec_550_intr_evcnt.ev_count++;
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#else
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if (DEC_550_MAX_IRQ != INTRCNT_DEC_550_IRQ_LEN)
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panic("dec_550 interrupt counter sizes inconsistent");
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intrcnt[INTRCNT_DEC_550_IRQ + irq]++;
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#endif
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if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) {
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alpha_shared_intr_stray(dec_550_pci_intr, irq,
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"dec 550 irq");
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if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq))
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dec_550_intr_disable(irq);
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}
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return;
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}
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#if NSIO
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if (vec >= 0x800) {
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sio_iointr(framep, vec);
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return;
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}
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#endif
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panic("dec_550_iointr: weird vec 0x%x\n", vec);
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}
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void
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dec_550_intr_enable(irq)
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int irq;
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{
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u_int64_t imask;
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int s;
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#if 0
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printf("dec_550_intr_enable: enabling %d\n", irq);
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#endif
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s = splhigh();
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alpha_mb();
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imask = REGVAL64(PYXIS_INT_MASK);
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imask |= (1UL << irq);
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REGVAL64(PYXIS_INT_MASK) = imask;
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alpha_mb();
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splx(s);
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}
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void
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dec_550_intr_disable(irq)
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int irq;
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{
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u_int64_t imask;
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int s;
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#if 0
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printf("dec_550_intr_disable: disabling %d\n", irq);
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#endif
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s = splhigh();
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alpha_mb();
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imask = REGVAL64(PYXIS_INT_MASK);
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imask &= ~(1UL << irq);
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REGVAL64(PYXIS_INT_MASK) = imask;
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alpha_mb();
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splx(s);
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}
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