305 lines
16 KiB
C
305 lines
16 KiB
C
/* $NetBSD: lan9118reg.h,v 1.3 2010/09/27 12:29:03 kiyohara Exp $ */
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/*
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* Copyright (c) 2008 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _LAN9118REG_H_
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#define _LAN9118REG_H_
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#define LAN9118_IOSIZE 0x100
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#define LAN9118_ID_9115 0x0115
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#define LAN9118_ID_9116 0x0116
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#define LAN9118_ID_9117 0x0117
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#define LAN9118_ID_9118 0x0118
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#define LAN9218_ID_9215 0x115a
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#define LAN9218_ID_9217 0x117a
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#define LAN9218_ID_9218 0x118a
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#define LAN9210_ID_9210 0x9210
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#define LAN9210_ID_9211 0x9211
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#define LAN9220_ID_9220 0x9220
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#define LAN9220_ID_9221 0x9221
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#define IS_LAN9118(id) ((id) >= LAN9118_ID_9115 && (id) <= LAN9118_ID_9118)
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#define IS_LAN9218(id) ((id) >= LAN9218_ID_9215 && (id) <= LAN9218_ID_9218)
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#define LAN9118_IPHY_ADDR 0x01 /* Internal PHY Address */
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#define LAN9118_RXDFIFOP 0x00 /* RX Data FIFO Port */
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#define LAN9118_RXDFIFOAP 0x04 /* RX Data FIFO Alias Ports */
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#define LAN9118_TXDFIFOP 0x20 /* TX Data FIFO Port */
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#define LAN9118_TXDFIFOAP 0x24 /* TX Data FIFO Alias Ports */
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#define LAN9118_RXSFIFOP 0x40 /* RX Status FIFO Port */
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#define LAN9118_RXSFIFOPEEK 0x44 /* RX Status FIFO PEEK */
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#define LAN9118_TXSFIFOP 0x48 /* TX Status FIFO Port */
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#define LAN9118_TXSFIFOPEEK 0x4c /* TX Status FIFO PEEK */
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/* System Control and Status Registers */
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#define LAN9118_ID_REV 0x50 /* Chip ID and Revision */
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#define LAN9118_ID_REV_ID(x) (((x) >> 16) & 0xffff)
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#define LAN9118_ID_REV_REV(x) ((x) & 0xffff)
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#define LAN9118_IRQ_CFG 0x54 /* Main Interrupt Configuration */
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#define LAN9118_IRQ_CFG_INT_DEAS(t) ((t) << 24) /* Intr Deassert Interval */
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#define LAN9118_IRQ_CFG_INT_DEAS_CLR (1 << 14) /* Intr Deass Intrval clr */
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#define LAN9118_IRQ_CFG_INT_DEAS_STS (1 << 13) /* Intr Deassert Status */
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#define LAN9118_IRQ_CFG_IRQ_INT (1 << 12) /* Master Interrupt */
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#define LAN9118_IRQ_CFG_IRQ_EN (1 << 8) /* IRQ Enable */
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#define LAN9118_IRQ_CFG_IRQ_POL (1 << 4) /* IRQ Polarity */
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#define LAN9118_IRQ_CFG_IRQ_TYPE (1 << 0) /* IRQ Buffer Type */
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#define LAN9118_INT_STS 0x58 /* Interrupt Status */
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#define LAN9118_INT_EN 0x5c /* Interrupt Enable Register */
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#define LAN9118_INT_SW_INT (1 << 31) /* Software Interrupt */
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#define LAN9118_INT_TXSTOP_INT (1 << 25) /* TX Stopped */
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#define LAN9118_INT_RXSTOP_INT (1 << 24) /* RX Stopped */
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#define LAN9118_INT_RXDFH_INT (1 << 23) /* RX Drppd Frm Cnt Halfway */
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#define LAN9118_INT_TX_IOC (1 << 21) /* TX IOC Interrupt */
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#define LAN9118_INT_RXD_INT (1 << 20) /* RX DMA Interrupt */
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#define LAN9118_INT_GPT_INT (1 << 19) /* GP Timer */
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#define LAN9118_INT_PHY_INT (1 << 18) /* PHY */
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#define LAN9118_INT_PME_INT (1 << 17) /* Power Management Event */
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#define LAN9118_INT_TXSO (1 << 16) /* TX Status FIFO Overflow */
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#define LAN9118_INT_RWT (1 << 15) /* Rcv Watchdog Time-out */
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#define LAN9118_INT_RXE (1 << 14) /* Receive Error */
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#define LAN9118_INT_TXE (1 << 13) /* Transmitter Error */
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#define LAN9118_INT_TDFO (1 << 10) /* TX Data FIFO Overrun */
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#define LAN9118_INT_TDFA (1 << 9) /* TX Data FIFO Available */
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#define LAN9118_INT_TSFF (1 << 8) /* TX Status FIFO Full */
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#define LAN9118_INT_TSFL (1 << 7) /* TX Status FIFO Level */
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#define LAN9118_INT_RXDF_INT (1 << 6) /* RX Dropped Frame Intr */
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#define LAN9118_INT_RSFF (1 << 4) /* RX Status FIFO Full */
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#define LAN9118_INT_RSFL (1 << 3) /* RX Status FIFO Level */
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#define LAN9118_INT_GPIOX_INT(x) (1 << (x)) /* GPIO[2:0] */
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/* 0x60 Reserved for future use */
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#define LAN9118_BYTE_TEST 0x64 /* Read-only byte order testing reg */
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#define LAN9118_BYTE_TEST_VALUE 0x87654321
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#define LAN9118_FIFO_INT 0x68 /* FIFO Level Interrupt */
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#define LAN9118_FIFO_INT_TXDAL(x) ((x) << 24) /* TX Data Available Lvl */
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#define LAN9118_FIFO_INT_TXSL(x) ((x) << 16) /* TX Status Level */
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#define LAN9118_FIFO_INT_RXSL(x) ((x) << 0) /* RX Status Level */
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#define LAN9118_RX_CFG 0x6c /* Receive Configuration */
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#define LAN9118_RX_CFG_RXEA_4B (0 << 30) /* RX End Alignment: 4 Byte */
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#define LAN9118_RX_CFG_RXEA_16B (1 << 30) /* 16 Byte */
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#define LAN9118_RX_CFG_RXEA_32B (2 << 30) /* 32 Byte */
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#define LAN9118_RX_CFG_RX_DMA_CNT(x) ((x) << 16) /* RX DMA Count */
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#define LAN9118_RX_CFG_RX_DUMP (1 << 15) /* Force RX Discard */
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#define LAN9118_RX_CFG_RXDOFF(x) ((x) << 8) /* RX Data Offset */
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#define LAN9118_TX_CFG 0x70 /* Transmit Configuration */
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#define LAN9118_TX_CFG_TXS_DUMP (1 << 15) /* Force TX Status Discard */
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#define LAN9118_TX_CFG_TXD_DUMP (1 << 14) /* Force TX Data Discard */
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#define LAN9118_TX_CFG_TXSAO (1 << 2) /* TX Status Allow Overrun */
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#define LAN9118_TX_CFG_TX_ON (1 << 1) /* Transmitter Enable */
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#define LAN9118_TX_CFG_STOP_TX (1 << 0) /* Stop Transmitter */
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#define LAN9118_HW_CFG 0x74 /* Hardware Configuration */
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#define LAN9118_HW_CFG_MBO (1 << 20)/* Must Be One */
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#define LAN9118_HW_CFG_TX_FIF_MASK (0xf << 16) /* TX FIFO Size */
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#define LAN9118_HW_CFG_TX_FIF_SZ(sz) ((sz) << 16)
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#define LAN9118_HW_CFG_PHY_CLK_SEL_MASK (3 << 5) /* PHY Clock Select */
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#define LAN9118_HW_CFG_PHY_CLK_SEL_IPHY (0 << 5) /* Internal PHY */
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#define LAN9118_HW_CFG_PHY_CLK_SEL_EMII (1 << 5) /* External MII Port */
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#define LAN9118_HW_CFG_PHY_CLK_SEL_CD (2 << 5) /* Clock Disabled */
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#define LAN9118_HW_CFG_SMI_SEL (1 << 4) /* Serial Mgmt Interface Sel */
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#define LAN9118_HW_CFG_EXT_PHY_DET (1 << 3) /* External PHY Detect */
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#define LAN9118_HW_CFG_EXT_PHY_EN (1 << 2) /* External PHY Enable */
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#define LAN9118_HW_CFG_SRST_TO (1 << 1) /* Soft Reset Timeout */
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#define LAN9118_HW_CFG_SRST (1 << 0) /* Soft Reset */
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#define LAN9118_RX_DP_CTL 0x78 /* RX Datapath Control */
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#define LAN9118_RX_DP_CTL_RX_FFWD (1 << 31)/* RX Data FIFO Fast Forward */
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#define LAN9118_RX_FIFO_INF 0x7c /* Receive FIFO Information */
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#define LAN9118_RX_FIFO_INF_RXSUSED(x) (((x) >> 16) & 0xff) /*Sts Used Space*/
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#define LAN9118_RX_FIFO_INF_RXDUSED(x) ((x) & 0xffff) /*Data FIFO Used Space*/
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#define LAN9118_TX_FIFO_INF 0x80 /* Transmit FIFO Information */
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#define LAN9118_TX_FIFO_INF_TXSUSED(x) (((x) >> 16) & 0xff) /*Sts Used Space*/
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#define LAN9118_TX_FIFO_INF_TDFREE(x) ((x) & 0xffff) /*Data FIFO Free Space*/
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#define LAN9118_PMT_CTRL 0x84 /* Power Management Control */
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#define LAN9118_PMT_CTRL_PM_MODE_MASK (3 << 12)
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#define LAN9118_PMT_CTRL_PM_MODE_D0 (0 << 12)
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#define LAN9118_PMT_CTRL_PM_MODE_D1 (1 << 12)
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#define LAN9118_PMT_CTRL_PM_MODE_D2 (2 << 12)
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#define LAN9118_PMT_CTRL_PHY_RST (1 << 10) /* PHY Reset */
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#define LAN9118_PMT_CTRL_WOL_EN (1 << 9) /* Wake-On-LAN Enable */
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#define LAN9118_PMT_CTRL_ED_EN (1 << 8) /* Energy-Detect Enable */
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#define LAN9118_PMT_CTRL_PME_TYPE (1 << 6) /* PME Buffer Type */
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#define LAN9118_PMT_CTRL_WUPS_NWUED (0 << 4) /* WAKE-UP Status: No Event */
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#define LAN9118_PMT_CTRL_WUPS_ED (1 << 4) /* WAKE-UP Status: Energy */
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#define LAN9118_PMT_CTRL_WUPS_WUD (2 << 4) /* WAKE-UP Status: Wake-up */
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#define LAN9118_PMT_CTRL_PME_IND (1 << 3) /* PME indication */
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#define LAN9118_PMT_CTRL_PME_POL (1 << 2) /* PME Polarity */
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#define LAN9118_PMT_CTRL_PME_EN (1 << 1) /* PME Enable */
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#define LAN9118_PMT_CTRL_READY (1 << 0) /* Device Ready */
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#define LAN9118_GPIO_CFG 0x88 /* General Purpose IO Configuration */
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#define LAN9118_GPIO_CFG_LEDX_EN(x) (1 << ((x) + 28)) /* LED[3:1] enable */
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#define LAN9118_GPIO_CFG_GPIO_INT_POL(p) (1 << ((p) + 24)) /* Intr Polarity */
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#define LAN9118_GPIO_CFG_EEPR_EN (7 << 20) /* EEPROM Enable */
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#define LAN9118_GPIO_CFG_GPIOBUFN(n) (1 << ((n) + 16)) /* Buffer Type */
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#define LAN9118_GPIO_CFG_GPDIRN(n) (1 << ((n) + 8)) /* Direction */
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#define LAN9118_GPIO_CFG_GPODN(n) (1 << (n)) /* GPIO Data (3,4 is WO) */
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#define LAN9118_GPT_CFG 0x8c /* General Purpose Timer Config */
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#define LAN9118_GPT_CNT 0x90 /* General Purpose Timer Count */
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/* 0x94 Reserved for future use */
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#define LAN9118_WORD_SWAP 0x98 /* WORD SWAP Register */
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#define LAN9118_FREE_RUN 0x9c /* Free Run Counter */
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#define LAN9118_RX_DROP 0xa0 /* RX Drop Frame Counter */
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#define LAN9118_MAC_CSR_CMD 0xa4 /* MAC CSR Synchronizer Command */
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#define LAN9118_MAC_CSR_CMD_BUSY (1 << 31)
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#define LAN9118_MAC_CSR_CMD_W (0 << 30)
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#define LAN9118_MAC_CSR_CMD_R (1 << 30)
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#define LAN9118_MAC_CSR_CMD_ADDRESS(a) ((a) & 0xff)
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#define LAN9118_MAC_CSR_DATA 0xa8 /* MAC CSR Synchronizer Data */
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#define LAN9118_AFC_CFG 0xac /* Automatic Flow Control Config */
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#define LAN9118_AFC_CFG_AFC_HI(x) ((x) << 16)
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#define LAN9118_AFC_CFG_AFC_LO(x) ((x) << 8)
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#define LAN9118_AFC_CFG_BACK_DUR(x) ((x) << 4)
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#define LAN9118_AFC_CFG_FCMULT (1 << 3) /* Flow Control on Multicast */
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#define LAN9118_AFC_CFG_FCBRD (1 << 2) /* Flow Control on Broadcast */
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#define LAN9118_AFC_CFG_FCADD (1 << 1) /* Flow Control on Addr Dec */
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#define LAN9118_AFC_CFG_FCANY (1 << 0) /* Flow Control on Any Frame */
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#define LAN9118_E2P_CMD 0xb0 /* EEPROM command */
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#define LAN9118_E2P_CMD_EPCB (1 << 31) /* EPC Busy */
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#define LAN9118_E2P_CMD_EPCC_READ (0 << 28) /* EPC Command: READ */
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#define LAN9118_E2P_CMD_EPCC_EWDS (1 << 28) /* EWDS */
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#define LAN9118_E2P_CMD_EPCC_EWEN (2 << 28) /* EWEN */
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#define LAN9118_E2P_CMD_EPCC_WRITE (3 << 28) /* WRITE */
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#define LAN9118_E2P_CMD_EPCC_WRAL (4 << 28) /* WRAL */
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#define LAN9118_E2P_CMD_EPCC_ERASE (5 << 28) /* ERASE */
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#define LAN9118_E2P_CMD_EPCC_ERAL (6 << 28) /* ERAL */
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#define LAN9118_E2P_CMD_EPCC_RELOAD (7 << 28) /* Reload */
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#define LAN9118_E2P_CMD_EPCTO (1 << 9) /* EPC Time-out */
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#define LAN9118_E2P_CMD_MACAL (1 << 8) /* MAC Address Loaded */
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#define LAN9118_E2P_CMD_EPCA(a) ((a) & 0xff) /* EPC Address */
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#define LAN9118_E2P_DATA 0xb4 /* EEPROM Data */
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/* 0xb8 - 0xfc Reserved for future use */
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/* MAC Control and Status Registers */
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#define LAN9118_MAC_CR 0x1 /* MAC Control Register */
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#define LAN9118_MAC_CR_RXALL (1 << 31) /* Receive All Mode */
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#define LAN9118_MAC_CR_RCVOWN (1 << 23) /* Disable Receive Own */
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#define LAN9118_MAC_CR_LOOPBK (1 << 21) /* Loopback operation Mode */
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#define LAN9118_MAC_CR_FDPX (1 << 20) /* Full Duplex Mode */
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#define LAN9118_MAC_CR_MCPAS (1 << 19) /* Pass All Multicast */
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#define LAN9118_MAC_CR_PRMS (1 << 18) /* Promiscuous Mode */
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#define LAN9118_MAC_CR_INVFILT (1 << 17) /* Inverse filtering */
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#define LAN9118_MAC_CR_PASSBAD (1 << 16) /* Pass Bad Frames */
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#define LAN9118_MAC_CR_HO (1 << 15) /* Hash Only Filtering mode */
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#define LAN9118_MAC_CR_HPFILT (1 << 13) /* Hash/Perfect Flt Mode */
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#define LAN9118_MAC_CR_LCOLL (1 << 12) /* Late Collision Control */
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#define LAN9118_MAC_CR_BCAST (1 << 11) /* Disable Broardcast Frms */
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#define LAN9118_MAC_CR_DISRTY (1 << 10) /* Disable Retry */
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#define LAN9118_MAC_CR_PADSTR (1 << 8) /* Automatic Pad String */
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#define LAN9118_MAC_CR_BOLMT (1 << 7) /* BackOff Limit */
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#define LAN9118_MAC_CR_DFCHK (1 << 5) /* Deferral Check */
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#define LAN9118_MAC_CR_TXEN (1 << 3) /* Transmitter enable */
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#define LAN9118_MAC_CR_RXEN (1 << 2) /* Receiver enable */
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#define LAN9118_ADDRH 0x2 /* MAC Address High */
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#define LAN9118_ADDRL 0x3 /* MAC Address Low */
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#define LAN9118_HASHH 0x4 /* Multicast Hash Table High */
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#define LAN9118_HASHL 0x5 /* Multicast Hash Table Low */
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#define LAN9118_MII_ACC 0x6 /* MII Access */
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#define LAN9118_MII_ACC_PHYA(a) ((a) << 11) /* PHY Address */
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#define LAN9118_MII_ACC_MIIRINDA(i) ((i) << 6) /* MII Register Index */
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#define LAN9118_MII_ACC_MIIWNR (1 << 1) /* MII Write */
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#define LAN9118_MII_ACC_MIIBZY (1 << 0) /* MII Busy */
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#define LAN9118_MII_DATA 0x7 /* MII Data */
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#define LAN9118_FLOW 0x8 /* Flow Control */
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#define LAN9118_FLOW_FCPT(t) ((t) << 16) /* Pause Time */
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#define LAN9118_FLOW_FCPASS (1 << 2) /* Pass Control Frame */
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#define LAN9118_FLOW_FCEN (1 << 1) /* Flow Control Enable */
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#define LAN9118_FLOW_FCBUSY (1 << 0) /* Flow Control Busy */
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#define LAN9118_VLAN1 0x9 /* VLAN1 Tag */
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#define LAN9118_VLAN2 0xa /* VLAN2 Tag */
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#define LAN9118_WUFF 0xb /* Wake-up Frame Filter */
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#define LAN9118_WUCSR 0xc /* Wake-up Control and Status */
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/* PHY Registers */
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#define LAN9118_MCSR 0x11 /* Mode Control/Status Register */
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#define LAN9118_MCSR_EDPWRDOWN (1 << 13) /* Energy Detect Power Down */
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#define LAN9118_MCSR_ENERGYON (1 << 1)
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#define LAN9118_SMR 0x12 /* Special Modes Register */
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#define LAN9118_SMR_PHYAD (0x01)
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#define LAN9118_SCSI 0x1b /* Special Control/Status Indications */
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#define LAN9118_SCSI_VCOOFF_LP (1 << 10)
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#define LAN9118_SCSI_XPOL (1 << 4) /* Polarity state */
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#define LAN9118_ISR 0x1d /* Interrupt Source Register */
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#define LAN9118_IMR 0x1e /* Interrupt Mask Register */
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#define LAN9118_I_ENERGYON (1 << 7)
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#define LAN9118_I_AUTONEGOCOMPL (1 << 6)
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#define LAN9118_I_REMOTEFAULT (1 << 5)
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#define LAN9118_I_LINKDOWN (1 << 4)
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#define LAN9118_I_AUTONEGOLPACK (1 << 3) /* AutoNego LP Acknowledge */
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#define LAN9118_I_PDF (1 << 2) /* Parallel Detection Fault */
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#define LAN9118_I_AUTONEGOPR (1 << 1) /* AutoNego Page Received */
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#define LAN9118_PHYSCSR 0x1f /* PHY Special Control/Status Reg */
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#define LAN9118_PHYSCSR_AUTODONE (1 << 12) /* AutoNego done indication */
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#define LAN9118_PHYSCSR_SI_10 (1 << 2) /* Speed Indication */
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#define LAN9118_PHYSCSR_SI_100 (2 << 2)
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#define LAN9118_PHYSCSR_SI_FDX (4 << 2)
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/* TX Command 'A' Format */
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#define LAN9118_TXC_A_IC (1 << 31) /* Interrupt on Completion */
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#define LAN9118_TXC_A_BEA_4B (0 << 24) /* Buffer End Alignment: 4B */
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#define LAN9118_TXC_A_BEA_16B (1 << 24) /* 16B */
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#define LAN9118_TXC_A_BEA_32B (2 << 24) /* 32B */
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#define LAN9118_TXC_A_DSO(x) ((x) << 16) /*Data Start Offset: bytes*/
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#define LAN9118_TXC_A_FS (1 << 13) /* First Segment */
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#define LAN9118_TXC_A_LS (1 << 12) /* Last Segment */
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#define LAN9118_TXC_A_BS(x) ((x) << 0) /* Buffer Size */
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/* TX Command 'B' Format */
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#define LAN9118_TXC_B_PT(x) ((x) << 16) /* Packet Tag */
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#define LAN9118_TXC_B_ACRCD (1 << 13) /* Add CRC Disable */
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#define LAN9118_TXC_B_DEFP (1 << 12) /* Dis Ether Frame Padding */
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#define LAN9118_TXC_B_PL(x) ((x) << 0) /* Packet Length */
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/* TX Status Format */
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#define LAN9118_TXS_PKTTAG(x) (((x) >> 16) & 0xff) /* Packet Tag */
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#define LAN9118_TXS_ES (1 << 15) /* Error Status */
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#define LAN9118_TXS_LOC (1 << 11) /* Loss Of Carrier */
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#define LAN9118_TXS_NC (1 << 10) /* No Carrier */
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#define LAN9118_TXS_LCOL (1 << 9) /* Late Collision */
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#define LAN9118_TXS_ECOL (1 << 8) /* Excessive Collision*/
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#define LAN9118_TXS_COLCNT(x) (((x) >> 3) & 0xf) /* Collision Count */
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#define LAN9118_TXS_ED (1 << 2) /* Excessive Deferral */
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#define LAN9118_TXS_DEFERRED (1 << 0) /* Deferred */
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/* RX Status Format */
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#define LAN9118_RXS_FILTFAIL (1 << 30) /* Filtering Fail */
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#define LAN9118_RXS_PKTLEN(x) (((x) >> 16) & 0x3fff) /* Packet Len */
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#define LAN9118_RXS_ES (1 << 15) /* Error Status */
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#define LAN9118_RXS_BCF (1 << 13) /* Broadcast Frame */
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#define LAN9118_RXS_LENERR (1 << 12) /* Length Error */
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#define LAN9118_RXS_RUNTF (1 << 11) /* Runt Frame */
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#define LAN9118_RXS_MCF (1 << 10) /* Multicast Frame */
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#define LAN9118_RXS_FTL (1 << 7) /* Frame Too Long */
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#define LAN9118_RXS_COLS (1 << 6) /* Collision Seen */
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#define LAN9118_RXS_FT (1 << 5) /* Frame Type */
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#define LAN9118_RXS_RWTO (1 << 4) /* Rcv Watchdog time-out */
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#define LAN9118_RXS_MIIERR (1 << 3) /* MII Error */
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#define LAN9118_RXS_DBIT (1 << 2) /* Drabbling Bit */
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#define LAN9118_RXS_CRCERR (1 << 1) /* CRC Error */
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#endif /* _LAN9118REG_H_ */
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