193 lines
6.0 KiB
C
193 lines
6.0 KiB
C
/* $NetBSD: aic6915var.h,v 1.4 2012/10/27 17:18:19 chs Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_AIC6915VAR_H_
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#define _DEV_IC_AIC6915VAR_H_
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#include <sys/callout.h>
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/*
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* Data structure definitions for the Adaptec AIC-6915 (``Starfire'')
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* PCI 10/100 Ethernet controller driver.
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*/
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/*
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* Transmit descriptor list size.
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*/
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#define SF_NTXDESC 256
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#define SF_NTXDESC_MASK (SF_NTXDESC - 1)
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#define SF_NEXTTX(x) ((x + 1) & SF_NTXDESC_MASK)
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/*
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* Transmit completion queue size. 1024 is a hardware requirement.
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*/
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#define SF_NTCD 1024
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#define SF_NTCD_MASK (SF_NTCD - 1)
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#define SF_NEXTTCD(x) ((x + 1) & SF_NTCD_MASK)
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/*
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* Receive descriptor list size.
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*/
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#define SF_NRXDESC 256
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#define SF_NRXDESC_MASK (SF_NRXDESC - 1)
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#define SF_NEXTRX(x) ((x + 1) & SF_NRXDESC_MASK)
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/*
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* Receive completion queue size. 1024 is a hardware requirement.
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*/
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#define SF_NRCD 1024
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#define SF_NRCD_MASK (SF_NRCD - 1)
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#define SF_NEXTRCD(x) ((x + 1) & SF_NRCD_MASK)
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/*
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* Control structures are DMA to the Starfire chip. We allocate them in
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* a single clump that maps to a single DMA segment to make several things
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* easier.
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*/
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struct sf_control_data {
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/*
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* The transmit descriptors.
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*/
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struct sf_txdesc0 scd_txdescs[SF_NTXDESC];
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/*
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* The transmit completion queue entires.
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*/
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struct sf_tcd scd_txcomp[SF_NTCD];
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/*
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* The receive buffer descriptors.
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*/
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struct sf_rbd32 scd_rxbufdescs[SF_NRXDESC];
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/*
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* The receive completion queue entries.
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*/
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struct sf_rcd_full scd_rxcomp[SF_NRCD];
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};
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#define SF_CDOFF(x) offsetof(struct sf_control_data, x)
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#define SF_CDTXDOFF(x) SF_CDOFF(scd_txdescs[(x)])
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#define SF_CDTXCOFF(x) SF_CDOFF(scd_txcomp[(x)])
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#define SF_CDRXDOFF(x) SF_CDOFF(scd_rxbufdescs[(x)])
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#define SF_CDRXCOFF(x) SF_CDOFF(scd_rxcomp[(x)])
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/*
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* Software state for transmit and receive descriptors.
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*/
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struct sf_descsoft {
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struct mbuf *ds_mbuf; /* head of mbuf chain */
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bus_dmamap_t ds_dmamap; /* our DMA map */
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};
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/*
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* Software state per device.
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*/
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struct sf_softc {
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device_t sc_dev; /* generic device information */
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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bus_space_handle_t sc_sh_func; /* sub-handle for func regs */
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bus_dma_tag_t sc_dmat; /* bus DMA tag */
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struct ethercom sc_ethercom; /* ethernet common data */
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int sc_iomapped; /* are we I/O mapped? */
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struct mii_data sc_mii; /* MII/media information */
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struct callout sc_tick_callout; /* MII callout */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
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/*
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* Software state for transmit and receive descriptors.
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*/
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struct sf_descsoft sc_txsoft[SF_NTXDESC];
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struct sf_descsoft sc_rxsoft[SF_NRXDESC];
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/*
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* Control data structures.
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*/
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struct sf_control_data *sc_control_data;
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#define sc_txdescs sc_control_data->scd_txdescs
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#define sc_txcomp sc_control_data->scd_txcomp
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#define sc_rxbufdescs sc_control_data->scd_rxbufdescs
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#define sc_rxcomp sc_control_data->scd_rxcomp
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int sc_txpending; /* number of Tx requests pending */
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uint32_t sc_InterruptEn; /* prototype InterruptEn register */
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uint32_t sc_TransmitFrameCSR; /* prototype TransmitFrameCSR reg */
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uint32_t sc_TxDescQueueCtrl; /* prototype TxDescQueueCtrl reg */
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int sc_txthresh; /* current Tx threshold */
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uint32_t sc_MacConfig1; /* prototype MacConfig1 register */
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uint32_t sc_RxAddressFilteringCtl;
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};
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#define SF_CDTXDADDR(sc, x) ((sc)->sc_cddma + SF_CDTXDOFF((x)))
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#define SF_CDTXCADDR(sc, x) ((sc)->sc_cddma + SF_CDTXCOFF((x)))
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#define SF_CDRXDADDR(sc, x) ((sc)->sc_cddma + SF_CDRXDOFF((x)))
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#define SF_CDRXCADDR(sc, x) ((sc)->sc_cddma + SF_CDRXCOFF((x)))
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#define SF_CDTXDSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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SF_CDTXDOFF((x)), sizeof(struct sf_txdesc0), (ops))
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#define SF_CDTXCSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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SF_CDTXCOFF((x)), sizeof(struct sf_tcd), (ops))
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#define SF_CDRXDSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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SF_CDRXDOFF((x)), sizeof(struct sf_rbd32), (ops))
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#define SF_CDRXCSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
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SF_CDRXCOFF((x)), sizeof(struct sf_rcd_full), (ops))
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#define SF_INIT_RXDESC(sc, x) \
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do { \
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struct sf_descsoft *__ds = &sc->sc_rxsoft[(x)]; \
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\
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(sc)->sc_rxbufdescs[(x)].rbd32_addr = \
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__ds->ds_dmamap->dm_segs[0].ds_addr | RBD_V; \
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SF_CDRXDSYNC((sc), (x), BUS_DMASYNC_PREWRITE); \
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} while (/*CONSTCOND*/0)
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#ifdef _KERNEL
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void sf_attach(struct sf_softc *);
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int sf_intr(void *);
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#endif /* _KERNEL */
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#endif /* _DEV_IC_AIC6915VAR_H_ */
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